9DB1200C IDT [Integrated Device Technology], 9DB1200C Datasheet - Page 4

• Manufacturer Part Number: 9DB1200C
• Description: Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
• Manufacturer: IDT [Integrated Device Technology]

Pin Description
IDT
PIN #
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
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Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
SMBDAT
FS1
BYPASS#/PLL
VTTPWRGD#/PD
DIF_6#
DIF_6
OE6#
GND
VDD
DIF_7#
DIF_7
OE7#
DIF_8#
DIF_8
OE8#
VDD
GND
DIF_9#
DIF_9
OE9#
DIF_10#
DIF_10
OE10#
GND
VDD
DIF_11#
DIF_11
OE11#
FS0
IREF
AGND
VDDA
PIN NAME
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Data pin of SMBUS circuitry, 5V tolerant
3.3V Frequency select latched input pin.
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
VTTPWRGD# is an active low input used to sample latched inputs and
allow the device to Power Up. PD is an asynchronous active high input
pin used to put the device into a low power state. The internal clocks and
PLLs are stopped.
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
3.3V Frequency select latched input pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Analog Ground pin for Core PLL
3.3V power for the PLL core.
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DESCRIPTION
1414F—06/30/10