5V49EE504NLGI8 IDT [Integrated Device Technology], 5V49EE504NLGI8 Datasheet - Page 13

• Manufacturer Part Number: 5V49EE504NLGI8
• Description: EEPROM PROGRAMMABLE CLOCK GENERATOR
• Manufacturer: IDT [Integrated Device Technology]

Each frame starts with a “Start Condition” and ends with an
“End Condition”. These are both generated by the Master
device.
External I
Progwrite
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
R/W
0 – Slave will be written by master
1 – Slave will be read by master
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a “1” bit.
S
IDT5V49EE504
EEPROM PROGRAMMABLE CLOCK GENERATOR
KEY:
SYMBOLS:
Address
7-bits
2
First Byte Transmitted on I
MSB
C Interface Condition
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition
1
1
R/W
0
7-bit slave address
0
ACK
1-bit
1
0
Command Code
8-bits: xxxx xx00
1
2
C Bus
0
LSB
R/W
Progwrite Command Frame
ACK from Slave
ACK
1-bit
13
Register
8-bits
ACK
1-bit
8-bits
Data
ACK
1-bit
IDT5V49EE504
CLOCK SYNTHESIZER
P
REV F 022310