9DB106 IDT [Integrated Device Technology], 9DB106 Datasheet - Page 10

• Manufacturer Part Number: 9DB106
• Description: Six Output Differential Buffer for PCIe Gen 2
• Manufacturer: IDT [Integrated Device Technology]

IDT
SMBusTable: Device Control Register, READ/WRITE ADDRESS (D4/D5)
SMBusTable: Output Enable Register
SMBusTable: Function Select Register
SMBusTable: Vendor & Revision ID Register
9DB106
Six Output Differential Buffer for PCIe Gen 2
®
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Six Output Differential Buffer for PCIe Gen 2
Byte 0
Byte 1
Byte 2
Byte 3
24,23
18,17
11,12
5,6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
PLL BW #adjust
PLL Enable
SW_EN
PCIEX5
PCIEX3
PCIEX2
PCIEX0
Name
Name
Name
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function Type
Bypasses PLL for
Control Function Type
Control Function Type
Control Function Type
Enables SMBus
Output Control
Output Control
Output Control
Output Control
Control of bits
REVISION ID
VENDOR ID
Selects PLL
Bandwidth
board test
(1:0)
10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLL controlled
(fan out mode)
PLL bypassed
by SMBus
registers
Low BW
Disable
Disable
Disable
Disable
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
by device pins
PLL controlled
PLL enabled
(ZDB mode)
High BW
Enable
Enable
Enable
Enable
1
1
1
1
-
-
-
-
-
-
-
-
9DB106
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
REV K 04/20/11