IDTIDT71P71604167BQ IDT [Integrated Device Technology], IDTIDT71P71604167BQ Datasheet - Page 14

• Manufacturer Part Number: IDTIDT71P71604167BQ
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Combined Read and Write Cycles
NOTE:
1. If a R/W is low on the next rising edge of K after a read request, the device automatically performs a NOP (No Operation.)
2. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent
18 Mb DDR II SRAM Burst of 2
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
the bus contention.
K
DQ
LD
CQ
R/W
CQ
K
SA
C
C
NOP
1
Qx1
tKHCH
tKHKL
tIVKH
tKLKH
tAVKH
Read A0
(burst of 2)
A0
2
tKHAX
tKHCH
tKHKH
tKHIX
Read A1
(burst of 2)
tCHCQV
tCHCQX
A1
tCHQX1
3
tCHQV
tKHKH
(NOTE 1)
Q00
NOP
4
Q01
tCHQX
tCHQV
NOP
(Note 1)
(NOTE 2)
Q10
5
Q11
6.42
tCHCQX
tCHCQV
14
Write A2
(burst of 2)
A2
6
tCHQX
tCHQZ
tDVKH
tKHKL
tKHDX
tKLKH
Write A3
(burst of 2)
D20
A3
7
D21
tKHKH
Read A4
(burst of 2)
tDVKH
A4
tKHDX
D30
8
tKHKH
D31
Commercial Temperature Range
9
tCQHQV
6112 drw09
Q40
tCQHQX
10
Q41