S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 144

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Note: The t
144
ADDRESS
UB#, LB#
CE1#
DQ
WE#
CE2
OE#
CE1#
V
DD
C2LH
READ DATA OUTPUT
specifies after V
Low
Figure 47. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
0V
t
OHAH
t
OES
t
t
BHZ
OH
DD
t
AS
reaches specified minimum level.
V
DD
WRITE ADDRESS
min
Figure 48. Power-up Timing #1
t
t
C2LH
WC
A d v a n c e
t
BW
WRITE DATA INPUT
t
DS
pSRAM Type 7
t
CHS
t
t
WR
DH
I n f o r m a t i o n
t
WHOL
t
ASO
t
t
CHH
BLZ
READ ADDRESS
t
AA
t
BA
t
RC
READ DATA OUTPUT
pSRAM_Type07_13_A0 May 4, 2004
t
OHAH
t
OH
t
BHZ