S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 108
S71GL256NB0
Manufacturer Part Number
S71GL256NB0
Description
Stacked Multi-chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GL256NB0.pdf
(147 pages)
- Current page: 108 of 147
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108
3 Volt
Symbol
twhz
twpc
twc
tcw
taw
tbw
twp
tdw
tow
tow
twr
tdh
tpc
tpa
tcp
tas
Performance Grade
Write cycle time
Chip select to
end of write
Address set up
Time
Address valid to
end of write
UB#, LB# valid
to end of write
Write pulse width
Write recovery
time
Write to output
High-Z
Data to write
time overlap
Data hold from
write time
End write to
output Low-Z
Write high pulse
width
Page read cycle
Page address
access time
Page write cycle
Chip select high
pulse width
Parameter
Version
Density
Min
55
45
45
45
45
40
0
0
0
5
x
x
x
x
A d v a n c e
8Mb pSRAM
-55
Max
25
x
x
pSRAM Type 1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B
I n f o r m a t i o n
Min
70
55
55
55
55
40
0
0
0
5
x
x
x
x
Asynchronous
8Mb pSRAM
-70
Max
25
x
x
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
70
70
70
70
55
25
pSRAM_Type01_12_A1 August 30, 2004
0
0
0
5
x
x
x
x
8Mb pSRAM
-70
Max
C
20
x
x
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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