S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 120

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Power Savings Modes (For 16M Page Mode, 32M and 64M Only)
120
CE#
Dat a Out
Page A ddr es s
Wor d A ddr es s
(A0 - A3 )
WE#
LB#, UB#
Partial Array Self Refresh (PAR)
(A4 - A 20)
There are several power savings modes.
The operation of the power saving modes ins controlled by the settings of bits
contained in the Mode Register. This definition of the Mode Register is shown in
Figure 28 and the various bits are used to enable and disable the various low
power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure xxx.
In this mode of operation, the internal refresh operation can be restricted to a
16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is
determined by the respective bit settings in the Mode Register. The register set-
tings for the PASR operation are defined in Table xxx. In this PASR mode, when
ZZ# is active low, only the portion of the array that is set in the register is re-
Partial Array Self Refresh
Temperature Compensated Refresh (64M)
Deep Sleep Mode
Reduced Memory Size (32M, 16M)
Figure 27. Timing Waveform of Page Mode Write Cycle (ZZ# = V
High-Z
t
AS
t
WC
t
LBW,
t
t
WP
A d v a n c e
CW
t
UBW
t
DW
pSRAM Type 1
t
DH
t
PGMAX
t
I n f o r m a t i o n
PWC
t
PDW
t
PDH
t
pSRAM_Type01_12_A1 August 30, 2004
PDW
IH
)
t
PDH