S71GL064A08 SPANSION [SPANSION], S71GL064A08 Datasheet - Page 7

• Manufacturer Part Number: S71GL064A08
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 80
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 81
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .82
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 92
Power Savings Modes . . . . . . . . . . . . . . . . . . . . . . 96
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Functional Description . . . . . . . . . . . . . . . . . . . . . 103
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 103
February 8, 2005 S71GL064A_00_A2
Output Load Circuit .......................................................................................... 81
Read Cycle ........................................................................................................... 92
Write Cycle ..........................................................................................................95
Partial Array Self Refresh (PAR) .................................................................... 96
Temperature Compensated Refresh (for 64Mb) ......................................97
Deep Sleep Mode ................................................................................................97
Reduced Memory Size (for 32M and 16M) ...................................................97
Other Mode Register Settings (for 64M) .....................................................97
ICC Characteristics ..........................................................................................100
Power Down ...................................................................................................... 103
Power Down Program Sequence .................................................................104
Address Key .......................................................................................................104
Table 13. 4Mb pSRAM Asynchronous .................................... 76
Table 14. 8Mb pSRAM Asynchronous .................................... 76
Table 15. 16Mb pSRAM Asynchronous .................................. 77
Table 16. 16Mb pSRAM Page Mode ...................................... 78
Table 17. 32Mb pSRAM Page Mode ...................................... 79
Table 18. 64Mb pSRAM Page Mode ...................................... 79
Figure 25. Output Load Circuit ............................................. 81
Table 19. 4Mb pSRAM Page Mode ........................................ 82
Table 20. 8Mb pSRAM Asynchronous .................................... 84
Figure 26. 16Mb pSRAM Asynchronous.................................. 86
Table 21. 16Mb pSRAM Page Mode ...................................... 87
Table 22. 32Mb pSRAM Page Mode ...................................... 89
Table 23. 64Mb pSRAM Page Mode ...................................... 91
Figure 27. Timing of Read Cycle
(CE# = OE# = V
Figure 28. Timing Waveform of Read Cycle (WE# = ZZ# = V
Figure 29. Timing Waveform of Page Mode
Read Cycle (WE# = ZZ# = V
Figure 30. Timing Waveform of Write Cycle
(WE# Control, ZZ# = V
Figure 31. Timing Waveform of Write Cycle
(CE# Control, ZZ# = V
Figure 32. Timing Waveform of Page Mode Write
Cycle (ZZ# = V
Figure 33. Mode Register..................................................... 98
Figure 34. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t
Care)................................................................................ 98
Figure 35. Deep Sleep Mode - Entry/Exit Timings (for 64M) ..... 99
Figure 36. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M) ............................................................. 99
Table 24. Mode Register Update and Deep Sleep Timings ....... 99
Table 25. Address Patterns for PASR (A4=1) (64M) ............... 99
Table 26. Deep ICC Characteristics (for 64Mb) .....................100
Table 27. Address Patterns for PAR (A3= 0, A4=1) (32M) ......100
Table 28. Address Patterns for RMS (A3 = 1, A4 = 1) (32M) ..100
Table 29. Low Power ICC Characteristics (32M) ....................101
Table 30. Address Patterns for PAR (A3= 0, A4=1) (16M) ......101
Table 31. Address Patterns for RMS (A3 = 1, A4 = 1) (16M) ..101
Table 32. Low Power ICC Characteristics (16M) ....................101
IH
IL
).............................................................. 96
, WE# = ZZ# = V
pSRAM Type 7
IH
IH
) ................................................... 95
) .................................................. 95
IH
) ........................................... 94
A d v a n c e
IH
)................................. 92
I n f o r m a t i o n
S71GL064A based MCPs
IH
) 93
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 105
Recommended Operating Conditions . . . . . . . . 105
Package Capacitance . . . . . . . . . . . . . . . . . . . . . 105
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 106
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .107
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Common Features . . . . . . . . . . . . . . . . . . . . . . . 120
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Functional Description . . . . . . . . . . . . . . . . . . . . 121
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 122
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 123
DC Operating Characteristics . . . . . . . . . . . . . . 123
AC Operating Conditions . . . . . . . . . . . . . . . . . . .126
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 126
Data Retention Characteristics . . . . . . . . . . . . . 127
Read Operation .................................................................................................107
Write Operation .............................................................................................. 108
Power Down Parameters ...............................................................................109
Other Timing Parameters ...............................................................................109
AC Test Conditions ..........................................................................................110
AC Measurement Output Load Circuits ....................................................110
Read Timings .........................................................................................................111
Write Timings ..................................................................................................... 113
Read/Write Timings ..........................................................................................116
Byte Mode ............................................................................................................121
Capacitance ......................................................................................................... 123
Test Conditions .................................................................................................126
Figure 37. AC Output Load Circuit – 16 Mb .......................... 110
Figure 38. AC Output Load Circuit – 32 Mb and 64 Mb .......... 110
Figure 39. Read Timing #1 (Basic Timing)........................... 111
Figure 40. Read Timing #2 (OE# Address Access ................. 111
Figure 41. Read Timing #3 (LB#/UB# Byte Access).............. 112
Figure 42. Read Timing #4 (Page Address Access after CE1# Control
Access for 32M and 64M Only)........................................... 112
Figure 43. Read Timing #5 (Random and Page Address Access for
32M and 64M Only).......................................................... 113
Figure 44. Write Timing #1 (Basic Timing) .......................... 113
Figure 45. Write Timing #2 (WE# Control) .......................... 114
Figure 46. Write Timing #3-1
(WE#/LB#/UB# Byte Write Control)................................... 114
Figure 47. Write Timing #3-3
(WE#/LB#/UB# Byte Write Control)................................... 115
Figure 48. Write Timing #3-4
(WE#/LB#/UB# Byte Write Control)................................... 115
Figure 49. Read/Write Timing #1-1 (CE1# Control).............. 116
Figure 50. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................ 116
Figure 51. Read / Write Timing #2 (OE#, WE# Control)........ 117
Figure 52. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control)......................................... 117
Figure 53. Power-up Timing #1 ......................................... 118
Figure 54. Power-up Timing #2 ......................................... 118
Figure 55. Power Down Entry and Exit Timing...................... 118
Figure 56. Standby Entry Timing after Read or Write ............ 119
Figure 57. Power Down Program Timing (for 32M/64M Only) . 119
4M Version F, 4M version G, 8M version C ..........................................121
8M Version D .................................................................................................122
Figure 58. AC Output Load ................................................ 126
Table 33. Read/Write Characteristics (V
Type 1 SRAM
CC
=2.7-3.3V) ........... 126
5