ZL50235GD ZARLINK [Zarlink Semiconductor Inc], ZL50235GD Datasheet
ZL50235GD
Related parts for ZL50235GD
ZL50235GD Summary of contents
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Features • Independent multiple channels of echo cancellation; from 16 channels of 64ms to 8 channels of 128ms with the ability to mix channels at 128ms or 64ms in any combination • Independent Power Down mode for each group of ...
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ZL50235 Description The ZL50235 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The ZL50235 architecture contains 8 groups of two echo cancellers (ECA and ECB) which can be configured to ...
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... Sout V IC0 DD1 SS DD1 V Rin V Rout V F0i SS SS DD1 DD2 SS DD1 SS DD1 DD1 DD2 DD1 SS DD1 SS ZL50235GD ...
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ZL50235 Pin Description PIN # PIN Name 208-Ball LBGA V A1, A3,A7,A11, A13, SS A15, A16, B2, B6, B8, B12, B14, B15, B16, C3, C5, C7, C9, C11, C12, C13, C14, C16, D4, D8, D10, D12, D13, E3, E4, E14, ...
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Data Sheet Pin Description (continued) PIN # PIN Name 208-Ball LBGA R11 DS R13 CS R5 R/W R7 DTA D0..D7 T2,T4,T6,T8,T9,T11, T13,T15 A0..A10 P16,N16,M16,L16,K16, J16,H16,G16,F16,E16, D16 ODE B13 Sout A8 Rout B9 Sin B11 Rin B7 B5 F0i A4 C4i ...
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ZL50235 Pin Description (continued) PIN # PIN Name 208-Ball LBGA Fsel H2 PLLVss1 K3 PLLVss2 PLLV K4 DD TMS M2 TDI M1 TDO N1 TCK P1 N2 TRST R3 RESET 1.0 Device Overview The ZL50235 architecture contains 16 echo cancellers ...
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Data Sheet Each echo canceller contains the following main elements (see Figure 4). • Adaptive Filter for estimating the echo channel • Subtractor for cancelling the echo • Double-Talk detector for disabling the filter adaptation during periods of double-talk • ...
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ZL50235 1.2 Double-Talk Detector Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. ...
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Data Sheet 1.4 Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50235 uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower ...
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ZL50235 The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original ...
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Data Sheet interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state. ...
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ZL50235 2.0 Device Configuration The ZL50235 architecture contains 16 echo cancellers divided into 8 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in ...
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Data Sheet Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 8 groups ...
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ZL50235 In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be “0”. Refer to Figure 4 and to Control Register 2 for bit description. 3.2 Bypass The Bypass state directly transfers PCM ...
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Data Sheet F0i ST-BUS F0i GCI interface Rin/Sin Rout/Sout Note: Refer to Figure 12 and Figure 13 for timing details. Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams Base ...
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ZL50235 6.0 Memory Mapped Control and Status registers Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a “per channel” basis to monitor and ...
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Data Sheet Group 0 Echo Cancellers Registers Group 1 Echo Cancellers Registers Groups 2 --> 6 Echo Cancellers Registers Group 7 Echo Cancellers Registers 6.4 Power Up Sequence On power up, the RESET pin must be held low for 100 ...
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ZL50235 6.6 Call Initialization To ensure fast initial convergence on a new call important to clear the Adaptive Filter. This is done by putting the echo canceller in bypass mode for at least one frame (125 s) and ...
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Data Sheet 7.0 JTAG Support The ZL50235 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is controlled by an Test Access Port (TAP) ...
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ZL50235 8.0 Register Description Power-up 00 Bit 7 Bit 6 Reset INJDis Reset When high, the power-up initialization is executed. This presets all register bits including this bit and clears the Adaptive Filter coefficients. INJDis When high, the noise injection ...
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Data Sheet Power-up 00 hex Bit 7 Bit 6 TDis PHDis TDis When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled ...
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ZL50235 Power-up 00 hex Bit 7 Bit 6 Reserve TD Reserve Reserved bit. TD Logic high indicates the presence of a 2100Hz tone. DTDet Logic high indicates the presence of a double-talk condition. Reserve Reserved bit. Reserve Reserved bit. Reserve ...
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Data Sheet Amplitude of MU 1.0 Flat Delay (FD ) 7-0 -16 2 9.0 Functional Description of Register Bits The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU) ...
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ZL50235 Power-up FB hex Bit 7 Bit 6 NLRun2 InjCtrl NLRun1 NLRun2 When high, the comfort noise level estimator actively rejects double-talk as being background noise. When low, the noise level estimator makes no such distinction. InjCtrl Selects which noise ...
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Data Sheet Power-up 54 hex Bit 7 Bit 6 0 SD2 0 Must be set to zero. SupDec These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast convergence state following a path change, Reset or ...
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ZL50235 Power-up N/A Bit 7 Bit 6 Bit 5 RP15 RP14 RP13 Power-up N/A Bit 7 Bit 6 Bit 5 RP7 RP6 RP5 These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The ...
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Data Sheet Power-up N/A Bit 7 Bit 6 Bit 5 EP15 EP14 EP13 Power-up N/A Bit 7 Bit 6 Bit 5 EP7 EP6 EP5 These peak detector registers allow the user to monitor the error signal peak level. The information ...
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ZL50235 ECA: Non-Linear Processor Threshold Register 2 Power-up 0C ECB: Non-Linear Processor Threshold Register 2 hex Bit 7 Bit 6 Bit 5 NLP15 NLP14 NLP13 ECA: Non-Linear Processor Threshold Register 1 Power-up E0 ECB: Non-Linear Processor Threshold Register 1 hex ...
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Data Sheet Power-up 44 hex Bit 7 Bit 6 Bit 5 0 Rin2 Rin1 Power-up 44 hex Bit 7 Bit 6 Bit 5 0 Sin2 Sin1 This register is used to select gain values on RIN, ROUT, SIN and SOUT. ...
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ZL50235 Power-up 00 Bit 7 Bit 6 WR_all ODE MIRQ Write all control bit: When high, Group 0-7 Echo Cancellers Registers are mapped into 0000 WR_all 0003F which is Group 0 address mapping. Useful to initialize the 8 Groups of ...
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Data Sheet Main Control Register 1 (EC Group 1) Main Control Register 2 (EC Group 2) Main Control Register 3 (EC Group 3) Main Control Register 4 (EC Group 4) Main Control Register 5 (EC Group 5) Main Control Register ...
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ZL50235 Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage (V DD1 2 Core Supply Voltage (V 3 Input Voltage 4 Input Voltage on any 5V Tolerant I/O pins 5 Continuous Current at digital outputs 6 Package power dissipation 7 Storage ...
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Data Sheet AC Electrical Characteristics - Voltages are with respect to ground (V ss Characteristics 1 CMOS Threshold 2 CMOS Rise/Fall Threshold Voltage High 3 CMOS Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated ...
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ZL50235 AC Electrical Characteristics Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS ...
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Data Sheet F0i C4i Sout/Rout Sin/Rin MCLK t FPW FPS FPH t SOD Bit 0, Channel 0 Bit 1, Channel SIS SIH Bit 0, Channel 0 Bit 1, Channel 0 Figure 13 - ...
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ZL50235 DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 16 - Motorola Non-Multiplexed Bus Timing 36 t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...