ZL50234GDC ZARLINK [Zarlink Semiconductor Inc], ZL50234GDC Datasheet - Page 18

• Manufacturer Part Number: ZL50234GDC
• Description: 8 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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6.5
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
The typical power consumption can be calculated with the following equation:
where 0
6.6
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125 s) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of Echo Canceller it is recommended that
the Echo cancellers are reset before any call progress tones are applied.
6.7
The ZL50234 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable
is detected and released.
Although the ZL50234 may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt when
a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status
Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address mapping
of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50234. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<3:0> allow Tone Disable to be masked or
unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section.
7.0
The ZL50234 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
ZL50234
Nb_of_groups
Power management
Call Initialization
Interrupts
JTAG Support
4.
P
C
= 9 * Nb_of_groups + 3.6, in mW
Zarlink Semiconductor Inc.
Data Sheet