ZL50234GDC ZARLINK [Zarlink Semiconductor Inc], ZL50234GDC Datasheet - Page 13

• Manufacturer Part Number: ZL50234GDC
• Description: 8 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Data Sheet
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a
transmission device or between two codecs for echo control on analog trunks.
2.3
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds
echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and the second
timeslot normally associated with ECB contains quiet code.
Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.
For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control
Register 1, Bit 0 must always be set to zero.
Table 4 shows the 4 groups of 2 cancellers that can each be configured into 64ms or 128ms echo tail capacity.
3.0
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
3.1
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet
code.
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be
“0”. Refer to Figure 4 and to Control Register 2 for bit description.
Extended Delay configuration
Echo Canceller Functional States
Mute
(quiet code)
Figure 8 - Extended Delay Configuration (128ms)
+Zero
echo
Table 2 - Quiet PCM Code Assignment
path A
PORT2
Rout
Sin
complement
LINEAR
0000
16 bits
2’s
channel A
channel A
ECA
hex
Zarlink Semiconductor Inc.
MAGNITUDE
Adaptive Filter
A-Law
SIGN/
80
-Law
(128 ms)
hex
-
+
FF
-Law
hex
CCITT (G.711)
PORT1
Sout
Rin
A-Law
D5
hex
ZL50234
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