ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 54

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.0
This guide will provide information and guidance for PCB layouts when using the ZL50130. Specific areas of
guidance are:
•
•
11.1
On the ZL50130 series of devices there are three high-speed data interfaces that need consideration when laying
out a PCB to ensure correct termination of traces and the reduction of crosstalk noise. The interfaces being:
•
•
•
In general the output drivers used in the ZL50130 are capable of driving modest capacitive loads with a reasonably
fast edge speed (<2.5 ns). Therefore these outputs are not designed to drive multiple loads, connectors,
backplanes or cables. It is recommended that the outputs are suitably terminated using a series termination through
a resistor as close to the output pin as possible. The purpose of the series termination resistor is to reduce
reflections on the line. The value of the series termination and the length of trace the output can drive will depend
on the driver output impedance, the characteristic impedance of the PCB trace (recommend 50 ohm), the
distributed trace capacitance and the load capacitance. As a general rule of thumb, if the trace length is less than
1/6th of the equivalent length of the rise and fall times, then a series termination may not be required.
For example:
Typical FR4 board delay = 6.8 ps/mm
Typical rise/fall time for a ZL50130 output = 2.5 ns
Therefore tracks longer than 61 mm will require termination.
As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is
crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace and therefore it
should be minimized in the layout. The voltage that the external fields cause is proportional to the strength of the
field and the length of the trace exposed to the field. Therefore to minimize the effect of crosstalk some basic
guidelines should be followed.
First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the
coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another
layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or
by placing guard traces between the signals usually held ground potential.
11.1.1
The timing of address, data and control are all related to the system clock which is also used by the external
SSRAM to clock these signals. Therefore the propagation delay of the clock to the ZL50130 and the SSRAM must
be matched to within 250 ps, worst case conditions. Trace lengths of theses signals must also be minimized
(<100 mm) and matched to ensure correct operation under all conditions.
High Speed Clock and Data, Outputs and Inputs
CPU_TA Output
External Memory Interface
MAC Interfaces
CPU Interface
High Speed Clock & Data Interfaces
Design and Layout Guidelines
External Memory Interface - special considerations during layout
the equivalent length of rise time = rise time (ps) / delay (ps/mm)
critical track length = (1/6) x (2500/6.8) = 61 mm
Zarlink Semiconductor Inc.
ZL50130
54
Data Sheet