ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 26

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

M1_RXDV
M1_RXER
M1_CRS
M1_TXCLK
M1_TXD[3:0]
M1_TXEN
Signal
I/O
I D
I D
I D
I U
O
O
Table 4 - MII Port 1 Interface Package Ball Definition
M26
L21
L23
L22
[3]
[2]
[1]
[0]
P23
R22
P21
T22
R21
Package Balls
Zarlink Semiconductor Inc.
ZL50130
MII Port 1
26
MII - M1_RXDV
Receive Data Valid. Active high.
This signal is clocked on the
rising edge of M1_RXCLK. It is
asserted when valid data is on
the M1_RXD bus.
MII - M1_RXER
Receive Error. Active high signal
indicating an error has been
detected. Normally valid when
M1_RXDV is asserted. Can be
used in conjunction with
M1_RXD when M1_RXDV
signal is de-asserted to indicate
a False Carrier.
MII - M1_CRS
Carrier Sense. This
asynchronous signal is asserted
when either the transmission or
reception device is non-idle. It is
active high.
MII Transmit Clock
Accepts the following
frequencies:
Transmit Data. Clocked on rising
edge of M1_TXCLK (MII).
MII - M1_TXEN
Transmit Enable. Asserted when
the MAC has data to transmit,
synchronously to M1_TXCLK
with the first pre-amble of the
packet to be sent. Remains
asserted until the end of the
packet transmission. Active
high.
25.0 MHz
Description
MII
100 Mbit/s
Data Sheet