ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 56

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.0
One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked
into the central office reference clock, and hence may be any value within the tolerance defined for that service.
The reverse link may also be independently timed, and operating at a slightly different frequency. In the
plesiochronous digital hierarchy the difference in clock frequencies between TDM links is compensated for using bit
stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network.
With a packet network, that connection between the ingress and egress frequency is broken, since packets are
discontinuous in time. From Figure 5, the TDM service frequency f
reproduced at the egress of the packet network. The consequence of a long-term mismatch in frequency is that the
queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is
slower or faster than the original. This will cause loss of data and degradation of the service.
The ZL50110/11/14 provides a per-stream clock recovery function to reproduce the TDM service frequency at the
egress of the packet network. Two schemes are employed, depending on the availability of a common reference
clock at each provider edge unit, within the ZL50110/11/14 - differential and adaptive. The clock recovery itself is
performed by software in the external processor, with support from on-chip hardware to gather the required
statistics.
6.1
For applications where the wander characteristics of the recovered clock are very important, such as when the
emulated circuit must be connected into the plesiochronous digital hierarchy (PDH), the ZL50110/11/14 also offers
a differential clock recovery technique. This relies on having a common reference clock available at each provider
edge point.
In a differential technique, the timing of data packet formation is sent relative to the common reference clock. Since
the same reference is available at the packet egress point and the packet size is fixed, the original service clock
frequency can be recovered. This technique is unaffected by any low frequency components in the packet delay
variation. The disadvantage is the requirement for a common reference clock at each end of the packet network,
which could either be the central office TDM clock, or provided by a global position system (GPS) receiver.
Differential Clock Recovery
Clock Recovery
LIU
Data
Source
Clock
ZL5011x
source
node
Timestamp
generation
Figure 17 - Differential Clock Recovery
Packets
Zarlink Semiconductor Inc.
ZL50110/11/14
Network
clock
PRS
56
Packets
service
ZL5011x
destination
node
Host CPU
at the customer premises must be exactly
Timestamp
extraction
recovery
Timing
DCO
Data
Dest'n
Clock
LIU
Data Sheet