ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 49

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

5.1
A diagram of the ZL50110/11/14 device is given in Figure 12, which shows the major data flows between functional
components.
5.2
There are numerous combinations that can be implemented to pass data through the ZL50110/11/14 device
depending on the application requirements. The Task Manager can be considered the central pivot, through which
all flows must operate.
The flow is determined by the Type field in the Task Message (see ZL50110/11/14 Programmers Model).
Block Diagram
Data and Control Flows
Data Flows
Control Flows
Recovery
Interface
Clock
TDM
Flow Number
Figure 12 - ZL50110/11/14 Data and Control Flows
1
2
3
4
5
6
7
8
9
Assembly
Formatter
Payload
Control
DMA
TDM
On-chip RAM and SSRAM Interface Controller
Table 21 - Standard Device Flows
Motorola PowerQUICC
Zarlink Semiconductor Inc.
Memory Management Unit
ZL50110/11/14
Off-chip Packet Memory
0-8 MBytes SSRAM
Manager
Protocol
Central
Engine
Task
49
TDM to (TM) to PE to (TM) to CPU
Host Interface
TDM to (TM) to PE to (TM) to PKT
PKT to (TM) to PE to (TM) to TDM
TM
Flow Through Device
Compatible
TDM to (TM) to CPU
CPU to (TM) to TDM
TDM to (TM) to PKT
PKT to (TM) to TDM
PKT to (TM) to CPU
CPU to (TM) to PKT
Transmit
Receive
Packet
Packet
JTAG Interface
JTAG Test
Controller
Interface
Admin.
Packet
Triple
MAC
Data Sheet