ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 33

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

M1_RXD[7:0]
M1_RXDV /
M1_RXD[8]
M1_RXER /
M1_RXD[9]
M1_CRS /
M1_Signal_Detect
M1_TXCLK
M1_TXD[7:0]
M1_TXEN /
M1_TXD[8]
Signal
Table 10 - MII Port 1 Interface Package Ball Definition (continued)
I/O
I U
I D
I D
I D
I U
O
O
[7]
[6]
[5]
[4]
M26
L21
L23
L22
[7]
[6]
[5]
[4]
P23
M25
P26
M24
P25
R24
P22
R23
T23
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
MII Port 1
33
N25
N24
R26
T26
R22
P21
T22
R21
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_RXCLK (GMII/MII) or the rising
edges of M1_RBC0 and M1_RBC1 (TBI).
GMII/MII - M1_RXDV
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M1_RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
TBI - M1_RXD[8]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
GMII/MII - M1_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M1_RXD[9]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
GMII/MII - M1_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active high.
TBI - M1_Signal Detect
Similar function to M1_CRS.
MII only - Transmit Clock
Accepts the following frequencies:
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_TXCLK (MII) or the rising edge
of M1_GTXCLK (GMII/TBI).
GMII/MII - M1_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M1_TXD[8]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
25.0 MHz
MII
Description
100 Mbps
Data Sheet