AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 53
AM79C970AKCW
Manufacturer Part Number
AM79C970AKCW
Description
PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C970AKCW.pdf
(219 pages)
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Master Abort
The PCnet-PCI II controller will terminate its cycle with a
Master Abort sequence if DEVSEL is not asserted within
4 clocks after FRAME is asserted. Master Abort is
treated as a fatal error by the PCnet-PCI II controller.
The PCnet-PCI II controller will reset all CSR locations
to their STOP_RESET values. The BCR and PCI con-
figuration registers will not be cleared. Any on-going net-
work transmission is terminated in an orderly sequence.
If less than 512 bits have been transmitted onto the net-
work, the transmission will be terminated immediately,
generating a runt packet. If 512 bits or more have been
transmitted, the message will have the current FCS
DEVSEL
FRAME
TRDY
C/BE
IRDY
PAR
GNT
CLK
REQ
AD
1
DEVSEL is sampled
2
ADDR
0111
Figure 22. Master Abort
3
P R E L I M I N A R Y
PAR
Am79C970A
4
inverted and appended at the next byte boundary to
guarantee
receiving station.
RMABORT (in the PCI Status register, bit 13) will be set
to indicate that the PCnet-PCI II controller has termi-
nated its transaction with a master abort. In addition,
SINT (CSR5, bit 11) will be set to ONE. When SINT is
set, INTA is asserted if the enable bit SINTE (CSR5, bit
10) is set to ONE. This mechanism can be used to in-
form the driver of the system error. The host can read
the PCI Status register to determine the exact cause
of the interrupt.
5
DATA
0000
6
an
PAR
FCS
7
error
8
is
9
detected
19436A-25
AMD
at
the
53
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