AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 36
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AM79C970AKCW
Manufacturer Part Number
AM79C970AKCW
Description
PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C970AKCW.pdf
(219 pages)
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read operation by setting the PREAD bit (BCR19, bit
14). While the EEPROM read is on-going, the
PCnet-PCI II controller will disconnect any slave access
where it is the target by asserting STOP together with
DEVSEL, while driving TRDY high. STOP will stay as-
serted until the host removes FRAME.
Note that I/O and memory slave accesses will only be
disconnected if they are enabled by setting the IOEN or
MEMEN bit in the PCI Command register. Without the
enable bit set, the cycles will not be claimed at all. Since
36
AMD
Figure 6. Disconnect Of Slave Cycle When Busy
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
PAR
CLK
AD
1
P R E L I M I N A R Y
ADDR
Am79C970A
CMD
2
PAR
H_RESET clears the IOEN and MEMEN bits, for the
automatic EEPROM read after H_RESET the discon-
nect only applies to configuration cycles.
A second situation where the PCnet-PCI II controller will
generate a PCI disconnect/retry cycle is when the host
tries to access any of the I/O resources right after having
read the Reset register. Since the access generates an
internal reset pulse of about 1 s in length, all further
slave accesses will be deferred until the internal reset
operation is completed.
3
DATA
BE
4
PAR
5
19436A-9
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