AM79C940KCW AMD [Advanced Micro Devices], AM79C940KCW Datasheet - Page 28
![no-image](/images/no-image-200.jpg)
AM79C940KCW
Manufacturer Part Number
AM79C940KCW
Description
Media Access Controller for Ethernet (MACE)
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C940KCW.pdf
(122 pages)
- Current page: 28 of 122
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sort of operation are bridges and routers. Lack of
perfect filtering in these applications forces the CPU to
be more involved in filtering and thus either slows the
forwarding rates achieved or forces the use of a more
powerful CPU.
DTV
The DTV pin is part of the host interface to the MACE
device. It is used to indicate that a read or write cycle to
the MACE device was successful. If DTV is not asserted
at the end of a cycle, the data transfer was not success-
ful. Basically, this will happen on a write to a full transmit
FIFO or a read from an empty receive FIFO. In general,
28
AMD
Am79C940
there are ways to ensure that a transfer is always valid
and so this pin is not required in many designs. For in-
stance, the TDTREQ and RDTREQ pins can be used to
monitor the state of the FIFOs to ensure that data trans-
fer only occurs at the correct times.
RXPOL
RXPOL is typically used to drive an LED indicating the
polarity of receive frames. This function is not neces-
sary for correct operation of the Ethernet and serves
strictly as a status indication to a user. The status of the
receive polarity is still available through the PHYCC
register.
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