AM79C940KCW AMD [Advanced Micro Devices], AM79C940KCW Datasheet - Page 102

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AM79C940KCW

Manufacturer Part Number
AM79C940KCW
Description
Media Access Controller for Ethernet (MACE)
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
AC WAVEFORMS
Note: Once the host detects the EOF output active from the MACE device (S2/S3 edge), if no other receive packet exists in
the RCVFIFO which meets the assert conditions for RDTREQ , the MACE device will deassert RDTREQ within 4 SCLK cycles
(S0/S1 edge). This is consistent for both 2 or 3 cycle read operations.
102
AMD
(EDSEL = 0)
(EDSEL = 1)
(EDSEL = 0)
(EDSEL = 1)
DBUS[15:0]
RDTREQ
ADD[4:0]
TC = 0
BE0-1
SCLK
SCLK
SCLK
SCLK
R/W
EOF
EOF
DTV
CS
S2
Host System Interface—3-Cycle Transmit FIFO/Register Write Timing
S2
TL
TL
S3
S3
31
33
TH
TH
S0
S0
S0
S0
Host System Interface—RDTREQ Read Timing
S1
S1
S1
S1
37
S2
S2
W0
W0
Word N
44
48
W1
W1
49
S2
S2
Am79C940
S3
S3
39
S0
S0
S0
S0
S1
S1
S1
S1
40
W0
W0
Word N+1
S2
S2
W1
W1
32
S3
S3
34
S2
S2
S0
S0
S3
S3
Note 1
S0
S0
42
S1
S1
Last Byte
or Word
W0
W0
45
W1
W1
S0
S0
43
34
S2 S3 S0
S2 S3 S0
S1
S1
41
16235C-28
16235C-29
S2
S2
S3
S3
38

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