ZL50022GAC ZARLINK [Zarlink Semiconductor Inc], ZL50022GAC Datasheet - Page 37

• Manufacturer Part Number: ZL50022GAC
• Description: Enhanced 4 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.0
This feature allows for fast initialization of the connection memory after power up.
10.1
1. Set MBPE (bit 3) in the Control Register (CR) from low to high.
2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded
3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The val-
The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.
Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0.
It takes at least two frame periods (250 µs) to complete a block program cycle.
MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.
MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.
Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the
MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other
device operations.
11.0
This device has two main operating modes - Master mode and Slave mode. Each operating mode has different
input/output clock and frame pulse setup requirements and usage.
If the device is programmed to work in Master mode, it is expected that the input clock and frame pulse will be
supplied from the embedded DPLL, either directly using the internal loopback mode or indirectly through external
loopback path. Sources and destinations of the device’s serial input and output data, respectively, have to be
synchronized with the device’s output clock and frame pulse. In Master mode, output clocks and frame pulses are
driven by the DPLL and they are always available with any of the specified frequencies.
The device can also operate in two different Slave modes: Divided Slave mode and Multiplied Slave mode. In either
Slave modes, output clocks and frame pulses are generated based on CKi and FPi. The difference is that, in
Value
Value
Bit
Bit
into CM_L.
ues stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values.
Memory Block Programming Procedure
Device Operation in Master Mode and Slave Modes
Connection Memory Block Programming
15
15
0
0
14
14
0
0
13
13
0
0
Table 6 - Connection Memory High After Block Programming
Table 5 - Connection Memory Low After Block Programming
12
12
0
0
11
11
0
0
10
10
0
0
Zarlink Semiconductor Inc.
9
0
9
0
ZL50022
8
0
8
0
37
7
0
7
0
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
BPD2
2
2
0
BPD1
Data Sheet
1
0
1
BPD0
0
0
0