ZL50022GAC ZARLINK [Zarlink Semiconductor Inc], ZL50022GAC Datasheet - Page 113
ZL50022GAC
Manufacturer Part Number
ZL50022GAC
Description
Enhanced 4 K Digital Switch with Stratum 4E DPLL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50022GAC.pdf
(121 pages)
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† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
1
2
3
4
5
6
7
(shares output pin
with FPo_OFF2)
FPo5 Output Pulse Width
FPo5 Output Delay from the FPo5 falling edge
to the output frame boundary
FPo5 Output Delay from the output frame
boundary to the FPo5 rising edge
CKo5 Output Clock Period
CKo5 Output High Time
CKo5 Output Low Time
CKo5 Output Rise/Fall Time
CKo5
FPo5
Characteristic
Output Frame Boundary
†
- CKo5 (19.44 MHz) Timing (Only when DPLL is active)
Figure 47 - CKo5 Timing Diagram (19.44 MHz)
t
t
t
t
FPW5
FODF5
CKP5
CKH5
Zarlink Semiconductor Inc.
ZL50022
113
t
rCK5
t
t
t
Sym.
FODR5
t
t
FODF5
t
FPW5
CKP5
CKH5
CKL5
, t
t
fCK5
fCK5
Min.
t
49
22
21
50
23
24
FODR5
t
CKL5
Typ.
51
25
25
51
25
25
‡
Max.
55
28
32
53
27
28
5
Units
ns
ns
ns
ns
ns
ns
ns
t
rCK5
V
V
Data Sheet
CT
CT
C
L
Notes
= 30 pF
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