ZL50015 ZARLINK [Zarlink Semiconductor Inc], ZL50015 Datasheet - Page 21

• Manufacturer Part Number: ZL50015
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL50015
Data Sheet
from CKi internally. In Master mode, the on-chip DPLL will drive the output data streams and provide output clocks
and frame pulses. Refer to Application Note ZLAN-120 for further explanation of the different modes of operation.
When the device is in Master mode, the DPLL is phase-locked to one of four DPLL reference signals, REF0 - 3,
which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz reference signal. The on-chip DPLL also offers jitter attenuation, reference switching, reference
monitoring, freerun and holdover functions. The jitter performance exceeds the Stratum 4E specification. The
intrinsic jitter of all output clocks is less than 1 ns (except for the 1.544 MHz output).
There are two slave modes for this device:
The first is the Divided Slave mode. In this mode, output streams are clocked by input CKi. Therefore the output
streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than
the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is
4.096 MHz, the output data rate cannot be higher than 2.048 Mbps. The second slave mode is called Multiplied
Slave mode. In this mode, CKi is used to generate a 16.384 MHz clock internally, and output streams are driven by
this 16.384 MHz clock. In Multiplied Slave mode, the data rate of output streams can be any rate, but output jitter
may not be exactly the same as input jitter.
A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate
in various modes under different switching configurations. Users can use the microprocessor port to perform
internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit
address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
4.0
Data Rates and Timing
The ZL50015 has 16 serial data inputs and 16 serial data outputs. Each stream can be individually programmed to
operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32
channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame.
The output streams can be programmed to operate as bi-directional streams. By setting BDL (bit 6) in the Internal
Mode Selection (IMS) register, the input streams 0 - 15 (STi0 - 15) are internally tied low, and the output streams 0
- 15 (STio0 - 15) are set to operate in a bi-directional mode.
The input data rate is set on a per-stream basis by programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input
Control Register 0 - 15 (SICR0 - 15). The output data rate is set on a per-stream basis by programming STO[n]DR3
- 0 (bits 3 - 0) in the Stream Output Control Register 0 - 15 (SOCR0 - 15). The output data rates do not have to
match or follow the input data rates. The maximum number of channels switched is limited to 1024 channels. If all
16 input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 4096 channels.
Memory limitations prevent the device from operating at this capacity. A maximum capacity of 1024 channels will
occur if four of the streams are operating at 16.384 Mbps, eight of the streams are operating at 8.192 Mbps or all
streams operating at 4.096 Mbps. With all streams operating at 2.048 Mbps, the capacity will be reduced to 512
channels. However, as each stream can be programmed to a different data rate, any combination of data rates can
be achieved, as long as the total channel count does not exceed 1024 channels. It should be noted that only full
stream can be programmed for use. The device does not allow fractional streams.
4.1
External High Impedance Control, STOHZ0 - 7
There are 16 external high impedance control signals, STOHZ0 - 7, that are used to control the external drivers for
per-channel high impedance operations. Only the first eight ST-BUS/GCI-Bus (STio0 - 7) outputs are provided with
corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot channels
based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin is high
and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 7 are enabled. When the ODE pin, OSB (bit
2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 7 are driven high, together with all the
ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any
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