ZL30414QGC ZARLINK [Zarlink Semiconductor Inc], ZL30414QGC Datasheet - Page 12

• Manufacturer Part Number: ZL30414QGC
• Description: SONET/SDH Clock Multiplier PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.2.3
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode
voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the V
as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for
LVDS applications.
3.2.4
The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as
close as possible to the LVPECL receiver.
CML to LVDS Interface
CML to LVPECL Interface
155.52 MHz
155.52 MHz
ZL30414
ZL30414
Driver
CML
Driver
GND
CML
GND
VCC
VCC
C155oP
C155oN
C155oP
C155oN
Figure 11 - CML to LVPECL Interface
Typical resistor values: R1 = 16 kΩ, R2 = 10 kΩ
Figure 10 - LVDS Termination
Typical resistor values: R1 = 82 Ω, R2 =130 Ω
Zarlink Semiconductor Inc.
+3.3 V
ZL30414
Z=50 Ω
Z=50 Ω
+3.3 V
0.1 uF
Z=50 Ω
Z=50 Ω
12
0.1 uF
10 nF
10 nF
10 nF
10 nF
VCC=+3.3 V
R1
R2
VCC=+3.3 V
R1
R2
R1
R2
CM
(common mode voltage)
R1
R2
LVDS
Receiver
100 Ω
LVPECL
Receiver
Data Sheet