ZL30117GGG ZARLINK [Zarlink Semiconductor Inc], ZL30117GGG Datasheet - Page 19

• Manufacturer Part Number: ZL30117GGG
• Description: SONET/SDH OC-48/OC-192 Line Card Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

(Hex)
Addr
2A -
43 -
3C
3D
3A
3B
3E
3F
4F
28
29
35
36
37
38
39
40
41
42
50
51
52
53
dpll_lock_holdover_status
Reserved
Reserved
p_enable
p_run
p_freq_0
p_freq_1
p_clk_offset90
Reserved
Reserved
p_offset_fine
p_fp_freq
p_fp_type
p_fp_offset_0
p_fp_offset_1
p_fp_offset_2
Reserved
sdh_enable
sdh_run
sdh_clk_div
sdh_clk_offset90
Register
Name
Programmable Synthesizer Configuration Registers
Table 5 - Register Map (continued)
Reset
Value
(Hex)
03
8F
0F
05
8F
0F
04
00
01
00
00
83
00
00
00
42
00
SDH Configuration Registers
Zarlink Semiconductor Inc.
ZL30117
DPLL lock and holdover status register
Leave as default
Leave as default
Control register to enable the p_clk and p_fp
outputs of the programmable synthesizer
Control register to generate p_clk, p_fp
Control register for the [7:0] bits of the N of
N*8k clk
Control register for the [13:8] bits of the N of
N*8k clk
Control register for the p_clk phase position
coarse tuning
Leave as default
Leave as default
Control register for the output/output phase
alignment fine tuning for the programmable
synthesizer
Control register to select the p_fp frame pulse
frequency
Control register to select p_fp type
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
Leave as default
Control register to enable sdh_clk and sdh_fp
Control register to generate sdh_clk and
sdh_fp
Control register for the sdh_clk frequency
selection
Control register for the sdh_clk phase position
coarse tuning
19
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R