ZL30117GGG ZARLINK [Zarlink Semiconductor Inc], ZL30117GGG Datasheet - Page 16

• Manufacturer Part Number: ZL30117GGG
• Description: SONET/SDH OC-48/OC-192 Line Card Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.6
The ZL30117 allows programmable static delay compensation for controlling input-to-output and output-to-output
delays of its clocks and frame pulses.
Both the SONET/SDH APLL and the Programmable Synthesizer can be configured to lead or lag the selected input
reference clock using the DPLL Fine Delay. The delay is programmed in steps of 119.2 ps with a range of -128 to
+127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative values delay the output
clock, positive values advance the output clock.
In addition to the delay introduced by the DPLL Fine Delay, the SONET/SDH APLL and programmable synthesizer
have the ability to add their own fine delay adjustments using the P Fine Delay and SDH Fine Delay. These delays
are also programmable in steps of 119.2 ps with a range of -128 to +127 steps.
In addition to these delays, the single-ended output clocks of the SONET/SDH and Programmable synthesizers
can be independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential
outputs can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame
pulses (sdh_clk, p_fp) can be independently offset with respect to each other using the FP Delay.
Configurable Input-to-Output and Output-to-Output Delays
DPLL
SDH Fine Delay
P Fine Delay
DPLL Fine Delay
Figure 7 - Phase Delay Adjustments
Zarlink Semiconductor Inc.
SONET/SDH
Programmable
Synthesizer
ZL30117
Synthesizer
Feedback
APLL
16
Coarse Delay
Coarse Delay
Diff Delay
FP Delay
FP Delay
p_clk
p_fp
sdh_clk
sdh_fp
diff_clk_p/n
Data Sheet