ZL30117GGG ZARLINK [Zarlink Semiconductor Inc], ZL30117GGG Datasheet - Page 12

• Manufacturer Part Number: ZL30117GGG
• Description: SONET/SDH OC-48/OC-192 Line Card Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.3
There are three reference clock inputs (ref0 to ref2) available to the DPLL. Reference selection can be controlled
using a built-in state machine or set in a manual mode.The selected reference input is used to synchronize the
output clocks.
In addition to the reference inputs, the DPLL has three optional frame pulse synchronization inputs (sync0 to
sync2) used to align the output frame pulses. The sync
= 0, 1, or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of
the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
When a frame pulse
signal is present at the
sync input, the DPLL
will align the output
frame pulses to the
output clock edge that is
aligned to the input
frame pulse.
Without a frame pulse
signal at the sync input,
the output frame pulses
will align to any arbitrary
cycle of its associated
output clock.
Ref and Sync Inputs
diff_clk/sdh_clk/p_clk
diff_clk/sdh_clk/p_clk
n = 0, 1, 2
n = 0, 1, 2
sync2:0
Figure 4 - Output Frame Pulse Alignment
ref2:0
Figure 3 - Reference and Sync Inputs
sdh_fp/p_fp
sdh/p_fp
sync
Zarlink Semiconductor Inc.
sync
ref
ref
ZL30117
n
n
n
n
- no frame pulse signal present
n
12
input is selected with its corresponding ref
DPLL
n
input, where n
Data Sheet