82V3391 IDT [Integrated Device Technology], 82V3391 Datasheet - Page 2

• Manufacturer Part Number: 82V3391
• Description: SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588
• Manufacturer: IDT [Integrated Device Technology]

DESCRIPTION
chronous Equipment Timing Source for Stratum 3, Stratum 4E, Stratum
4, SMC, EEC-Option1, EEC-Option2 clocks in SONET / SDH / Synchro-
nous Ethernet equipment, DWDM and Wireless base station.
clock from Synchronous Ethernet, STM-N or OC-n, PDH network syn-
chronization timing and external synchronization reference timing.
and highly configurable path to provide system clock for node timing
synchronization within a SONET / SDH / Synchronous Ethernet network.
The T4 path is simpler and less configurable for equipment synchroniza-
tion. The T4 path locks independently from the T0 path or locks to the T0
path.
path. Both the T0 and T4 paths support three primary operating modes:
Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to
the master clock. In Locked mode, the DPLL locks to the selected input
clock. In Holdover mode, the DPLL resorts to the frequency data
Description
IDT82V3391 PRODUCT BRIEF
The IDT82V3391 is an integrated, single-chip solution for the Syn-
The device supports several types of input clock sources: recovered
The device consists of T0 and T4 paths. The T0 path is a high quality
An input clock is automatically or manually selected for T0 and T4
SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588
2
acquired in Locked mode. Whatever the operating mode is, the DPLL
gives a stable performance without being affected by operating condi-
tions or silicon process variations.
SONET and Ethernet Clocks
560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different
settings cover all SONET / SDH clock synchronization requirements.
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
interface. The device supports six microprocessor interface modes:
EPROM, Multiplexed, Intel, Motorola, I2C and Serial.
this application, two devices should be used together to enable system
protection against single chip failure.
There are 2 high performance APLLs that can be used for low jitter
The device provides programmable DPLL bandwidths: 0.5 mHz to
A highly stable input is required for the master clock in different appli-
All the read/write registers are accessed through a microprocessor
In general, the device can be used in Master/Slave application. In
March 5, 2012