82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 81

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

PRIORITY_TABLE1_STS - Priority Status 1 *
Programming Information
IDT82V3352
Address: 4EH
Type: Read
Default Value: 00000000
ORITY_VALIDA
HIGHEST_PRI
7 - 4
3 - 0
Bit
TED3
7
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
ORITY_VALIDA
HIGHEST_PRI
TED2
6
Name
ORITY_VALIDA
HIGHEST_PRI
TED1
5
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
These bits indicate the selected input clock.
0000: No input clock is selected. (default)
0001, 0010: Reserved.
0011: IN1_CMOS is selected.
0100: IN2_CMOS is selected.
0101: IN1_DIFF is selected.
0110: IN2_DIFF is selected.
0111, 1000: Reserved.
1001: IN3_CMOS is selected.
1010 ~ 1111: Reserved.
ORITY_VALIDA
HIGHEST_PRI
TED0
4
81
CURRENTLY_S
ELECTED_INP
UT3
3
CURRENTLY_S
ELECTED_INP
Description
UT2
2
SYNCHRONOUS ETHERNET WAN PLL
CURRENTLY_S
ELECTED_INP
UT1
1
CURRENTLY_S
ELECTED_INP
March 23, 2009
UT0
0