ZL30106_05 ZARLINK [Zarlink Semiconductor Inc], ZL30106_05 Datasheet - Page 28

• Manufacturer Part Number: ZL30106_05
• Description: SONET/SDH/PDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

If a clock and frame pulse pair is used for synchronization, the TIE correction value should be cleared by keeping
the TIE_CLR pin low for at least 15 ns. Otherwise a static phase offset may remain between the output frame pulse
and the REF_SYNC frame pulse. Reference switching from one REF- REF_SYNC pair to the other REF-
REF_SYNC pair does not activate the TIE correction circuit and the ZL30106 will align the output frame pulse to the
new REF_SYNC frame pulse. In that case the MTIE can be as large as 250 µs for a 2 kHz REF_SYNC signal and
62.5 µs for an 8 kHz REF_SYNC signal. Reference switching from a REF- REF_SYNC pair to a single REF input
however, is hitless unless the TIE_CLR pin is kept low.
If a REF - REF_SYNC pair is used as the reference then if the ZL30106 transitions from Holdover to Normal mode,
the TIE correction circuit will not be activated and the PLL will align its output clock and frame pulse with the input
REF and REF_SYNC pair.
REF_SYNC0/1 = 2 kHz
REF0/1 = C19o
REF_SYNC0/1 = 8 kHz
REF0/1 = C8o
F2ko
C19o
C8o
F8o
Figure 18 - Examples of REF & REF_SYNC to Output Alignment
Zarlink Semiconductor Inc.
ZL30106
aligned
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aligned
Data Sheet