SI2107-X-FM SILABS [Silicon Laboratories], SI2107-X-FM Datasheet - Page 34

• Manufacturer Part Number: SI2107-X-FM
• Description: SATELLITE RECEIVER FOR DVB-S/DSS WITH QUICKLOCK AND QUICKSCAN
• Manufacturer: SILABS [Silicon Laboratories]

7. I
The I
monitoring of all internal registers. The Si2107/08/09/10
supports the 7-bit addressing procedure and is capable
of operating at rates up to 400 kbps. Individual data
transfers to and from the device are 8-bits. The I
consists of two wires: a serial clock line (SCL) and a
serial data line (SDA). The device always operates as a
bus slave. Read and write operations are performed in
accordance with the I
following sequences.
The first byte after the START condition consists of the
slave address (SLAVE ADR, 7-bits) of the target device.
The slave address is configured during a hard reset by
setting the voltage on the ADDR pin. Possible slave
addresses and their corresponding ADDR voltages are
listed in Table 18.
Four addresses are available, allowing up to four
devices to share the same I
determines the direction of data transfer. During a read
operation, data is sent from the device to the bus
Read O peration
W rite Operation
S
S
A = Acknowledge
R = Read (1)
W = W rite (0)
Fixed Address
2
2
M aster
Table 18. I
C bus interface is provided for configuration and
C Control Interface
11010
11010
11010
11010
SLAVE ADR
SLAVE ADR
Slave
2
S = START condition
P = STOP condition
S
C Slave Address Selection
r
= Repeated START condition
LSBs
W
W
2
00
01
10
11
C-bus specification and the
A
A
2
C bus. The R/W bit
ADDR Voltage (V)
DATA (ADR)
DATA (ADR)
2/3 x V
1/3 x V
0 (pulldown)
V
3.3
Figure 22. I
(pullup)
3.3
3.3
±10%
±10%
Preliminary Rev. 0.81
2
C bus
A
A
2
C Interface Protocol
S
S
r
r
or P
or P
master. During a write, data is sent from the bus master
to the device. The field labeled “DATA (ADR)” must
contain the 8-bit address of the target register. The data
to be transferred to or from the target register must be
placed in the following 8-bit “DATA” field. When the
auto-increment feature is enabled, INC_DS, the target
register address, is automatically incremented for
subsequent data transfers until a STOP condition ends
the operation.
Some registers in the device are larger than the 8-bit
DATA field permitted by I
into 8-bit addressable chunks that are uniquely
identified by a positional suffix. The suffix L indicates the
low-byte; the suffix M indicates the middle-byte (for 24-
bit registers only), and the suffix H indicates the high-
byte.
To read a multibyte register as a single unit, the low byte
must be read first. This forces the device to sample and
hold the contents of the remaining bytes until the
multibyte read is complete. If a STOP condition occurs
before the operation is complete, the buffered data is
discarded.
To write a multibyte register as a single unit, the low
byte must be written first. All bytes must be transferred
to the device before the multibyte value is recorded. If a
STOP condition occurs before the operation is
complete, the buffered data is discarded.
The slave address consists of a fixed part and a
programmable part. The voltage of the ADDR pin is
used to set the two least significant bits of the address
during device power-up according to the table below.
This enables up to four devices to share the same I
bus.
SLAVE ADR
SLAVE ADR
Si2107/08/09/10
R
W
A
A
2
C. These registers are split
n bytes + ack
n bytes + ack
DATA
DATA
A/A
A/A
P
2
P
34
C