SI2704-A10 SILABS [Silicon Laboratories], SI2704-A10 Datasheet
SI2704-A10
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SI2704-A10 Summary of contents
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... Table top and portable radios Description The Si2704/05/06/07 EMI mitigating 2.1 digital audio processing Class D amplifier integrates a power stage, PWM DAC, and digital audio processing (DAP) for simplified, low cost, power efficient system designs in consumer audio electronics. The digital input amplifier features delta-sigma PWM and ...
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... Si2704/05/06/07-A10 2 Rev. 0.6 ...
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... Tone and Alert Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7. Fault Detection and Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8. Power Supply and Grounding Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.10. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1. 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2. 48-Pin eTQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Si2704/05/06/07-A10 Rev. 0.6 Page 3 ...
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... Si2704/05/06/07-A10 8.1. 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2. 48-Pin eTQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9. Package Markings (Top Marks 9.1. Si2707 Top Mark (QFN 9.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3. Si2707 Top Mark (eTQFP 9.4. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4 Rev. 0.6 ...
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... Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. For input pins SCLK, SDIO, DCLK, DFS, DIN, RST, OUTSEL, MFPx. Si2704/05/06/07-A10 1 Test Condition V ...
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... Si2704/05/06/07-A10 Table 3. DC Characteristics—Supplies and Interfaces (V = 2 1. Parameter Symbol Start Up Time T ONSB T ON_SLP T ON_PD Active Mode Quiescent I PQ Supply Current IOQ Standby Mode Supply I PSTB Current I DSTB I IOSTB Sleep Mode Supply I PSLP Current I DSLP I IOSLP ...
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... Notch Attenuation Notes: 1. Measured at filter output. Power measured at the chip output is greater. 2. Guaranteed by characterization. 3. Measured relative to the integrated noise floor in Spread mode. Guaranteed by characterization. 4. Does not include filter efficiency losses. Si2704/05/06/07-A10 = –20 to +85 ° Symbol Test Condition ...
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... Si2704/05/06/07-A10 Table 5. AC Characteristics—Class D Amplifier (Continued 2 1. Power Supply Rejection Ratio Crosstalk 4 Efficiency Output Pulse Repetition Frequency Notes: 1. Measured at filter output. Power measured at the chip output is greater. 2. Guaranteed by characterization. 3. Measured relative to the integrated noise floor in Spread mode. Guaranteed by characterization. ...
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... SDIO Input to SCLK ↓ Hold SDIO output delay SCLK input to SDIO ↑ Setup (STOP) STOP to START Time SDIO Output Fall Time SDIO Input, SCLK Rise/Fall Time Capacitive Loading Pulse Width Rejected by Input Filter Si2704/05/06/07-A10 Symbol Test Min Condition f 0 SCL t 1 ...
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... Si2704/05/06/07-A10 Table 9. 2-Wire Control Interface Address Selection CLKO Startup Voltage (Pin Table 10. Reset Timing Characteristics (V = 1. -20 to +85 °C, unless otherwise noted Parameter CLKO Setup Time to RST↑ CLKO Hold Time after RST↑ Figure 2. Reset Timing Parameters for Configuration Mode Select ...
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... SDIO 30% START t r:IN Figure 3. 2-Wire Control Interface Read and Write Timing Parameters SCLK SDIO A6-A0, 0 (Write) START ADDRESS + R/W SDIO A6-A0, 1 (Read) START ADDRESS + R/W Figure 4. 2-Wire Control Interface Read and Write Timing Diagram Si2704/05/06/07-A10 HIGH t r:IN f: HD:DAT SU:DAT PD:DAT Command 7-0 ACK DATA ...
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... Si2704/05/06/07-A10 Table 11. Reference Clock and Crystal Characteristics (V = 2 1. Parameter Reference Clock, Pin XTLI 1 Supported Frequencies Frequency Tolerance 2 Jitter Tolerance High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Crystal oscillator, Pins XTLI, XTLO ...
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... AUXOL Figure 5. Typical Application Schematic Table 12. Typical Application Schematic Bill of Materials Component C1, C2, C3, C4 C15, C16, C17, C18 C5, C6 L1, L2, L3, L4 Note: When using the ferrite bead output filter with AM radio, shielded cable is recommended. Si2704/05/06/07-A10 C9 0.1 uF C10 0 OUTPL 17 OUTNL 16 ...
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... Si2704/05/06/07-A10 3. Typical System Configurations 2.7–3.6 V Supply Dock Dock I/F Stereo Line ADC In System MCU User I/F Figure 6. Basic PMP Dock System Configuration 2.7–3.6 V Supply Digital Media Controller Dock Radio Tuner Dock I/F Si473x-D Stereo Line ADC In System MCU User I/F Figure 7. PMP Dock with Radio and Digital Media Controller System Configuration ...
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... Figure 8. Stereo 2-Way Speaker System Configuration Analog Audio 1 Analog Audio 2 Receiver & Mux Digital Audio Audio Processor DVI/PC Delay Control Audio From PMP dock Figure 9. TV Sound Bar System Configuration Si2704/05/06/07-A10 External Subwoofer AUXOL L Midrange L R Midrange R OUTSEL L Tweeter L R Tweeter R OUTSEL HPDET AUXOL Headphone ...
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... Control Figure 10. Functional Block Diagram The Si2704/05/06/07 EMI mitigating 2 Class D audio amplifier integrates a stereo power stage, PWM DAC, and digital signal processor (DSP) to enable simplified, low cost, power efficient system designs in consumer audio electronics. The digital input amplifier features delta-sigma PWM for high quality audio while innovative EMI mitigation technology manages PWM switching noise to suppress peak emissions more than 20 dB while providing co-existence with AM/FM radio tuners ...
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... Fractional Mode PWM, the common mode switching energy and harmonics are shifted down in frequency by 50%, and are located at F The spectral shifting mode can be programmed dynamically by setting property PWM_CONFIG during normal operation without adversely affecting the internal audio processing or the amplified audio signal integrity. Si2704/05/06/07-A10 x (2n–1)/2. C Rev. 0.6 ...
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... Si2704/05/06/07-A10 Figure 11. PWM CM Spectrum for Integer Mode PWM Figure 12. PWM CM Spectrum for Fractional Mode PWM 4.1.2.3. Spectral Spreading Spread mode PWM can be used to spread PWM common mode switching energy resulting in a peak energy suppression greater than all frequencies. This Spectral Shaping feature is useful for mitigating EMI radiation and eliminating inductors for filter-less applications ...
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... Figure 13. PWM CM Spectrum for Spread Mode PWM with Noise-Free Notch 4.2. Operating Modes The Si2704/05/06/07 features four operating modes: one active mode (Active) and three low power modes (Standby, Sleep and Power Down). The low power modes differ on power consumption and wake up times, providing the flexibility to meet system design requirements. See Table 3, “ ...
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... Si2704/05/06/07-A10 POWER_DOWN Sleep Mode 4.2.2. Standby Mode Standby Mode is a reduced power state where the register states are preserved and the 2-Wire interface is fully operational, allowing for new parameters and configuration settings to be programmed even though the amplifier output is powered down. This state has the shortest wake-up time relative to the other low power modes. If the buffered reference clock output (CLKO) is enabled, the timing generation circuitry remains active ...
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... MFP pin function is established using the MFP_PIN_CFG command. Refer to the “AN469: Si270x Programming Guide” for more information on the options and settings requested for operation of the multi function pins. Si2704/05/06/07-A10 Functional Description OUTSEL Tri-level output mode select ...
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... Si2704/05/06/07-A10 4.3.2. Output Mode Configuration (Si2705/07 only) The Si2705/07 can be programmed via 2-Wire or configured using the OUTSEL MFP to operate in three different output modes: 2.1 mode, 2.0 mode and aux out mode, with the 2.0 mode being the default. If OUTSEL is not configured as OUTSEL, these output modes can instead be programmed by setting the argument OUTSEL_MODE of the ACTIVATE command. Refer to the “ ...
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... I connected to ground. 4.4.2. Reference Clock Output The Si2704/05/06/07 may provide a buffered output clock to be used as reference for external circuits when the chip is programmed for either Active or Standby mode. The clock output frequency and synchronization source is programmable. ...
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... Si2704/05/06/07-A10 2 4.5. Digital Audio I S Interface The Si270x receives digital audio data using its I an input or output while DIN is restricted to input only, and all three can be configured to operate in either master or slave mode. Only one output is supported at a time. All data ports operate synchronously from a single bit-clock and frame-clock signal. During normal operation, the crossbar mixer outputs are independently programmed linear combination of any of the channels from the configured inputs with a scaling range from – ...
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... DOUT DSP 0x06 n n-1 st (MSB at 1 rising edge) MSB 1 DCLK DOUT n DSP 0x04 nd (MSB at 2 rising edge) MSB Figure 19. DSP Digital Audio Format Si2704/05/06/07-A10 LEFT CHANNEL 1 DCLK n MSB LSB 2 Figure 17 Digital Audio Format LEFT CHANNEL MSB ...
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... Si2704/05/06/07-A10 4.6. Digital Audio Processing (DAP) The Si270x implements programmable digital audio processing which features volume control, dynamic range compressor (DRC), and audio filtering such as tone control, parametric equalization, crossover, and de-emphasis. The three channel digital audio processing chain for the Si2707 is shown in Figure 20. ...
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... BASS_CORNER_FREQ (for bass) and TREBLE_CORNER_FREQ (for treble). Gain can be adjusted from – steps by setting properties BASS_BOOST_CUT (for bass) and TREBLE_BOOST_CUT (for treble). Figure 22 shows the characteristics of the bass and treble shelving filters. Gain Boost 1 Cut Figure 22. Generic Bass/Treble Shelving Filter Characteristics Si2704/05/06/07-A10 ...
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... Si2704/05/06/07-A10 4.6.3. De-Emphasis (Si2706/07 only) The Si2706/07 features a de-emphasis filtering option in order to be able to process recorded audio that for noise reasons has been subject to 50/15 µs pre-emphasis. The 50/15 µs filter implemented has corner frequencies at 3.183 kHz and 10.610 kHz. 4.6.4. Crossover Filter (Si2706/07 only) The Si2706/07 features a programmable frequency 12 dB/octave Linkwitz-Riley type crossover filter that provides separation of the low and high frequency content of the audio signal ...
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... DRC_LOOKAHEAD_TIME allows setting the look ahead time that permits the DRC circuit to adjust the compression to sudden level changes thus preventing the clipping of the fast changing signal. Refer to “AN503: Si270x Class-D Amplifier—Dynamic Range Compressor Use” for additional information. Si2704/05/06/07-A10 Rev. 0.6 29 ...
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... Si2704/05/06/07-A10 Figure 24. Time Domain Characteristics of the Audio Dynamic Range Controller 4.6.7. Hard Signal Limiter The device implements a hard limiter to avoid exceeding the maximum modulation rate of the amplifier. The hard limiter is always enabled. 4.6.8. DC Notch Filter A dc notch filter with corner frequency is implemented as the final function in the signal processing chain to remove any dc component from the output signal ...
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... Subsequent sections of this data sheet mention many of the commands and properties that are used to alter different functions. More information on the complete list of programming modes of operation and properties can be found in the “AN469: Si270x Programming Guide.” Si2704/05/06/07-A10 , should be decoupled with 0.1 µF capacitors soldered as close to the device IO Rev ...
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... Si2704/05/06/07-A10 5. Commands and Properties Table 16 and Table 17 are the summary of commands and properties for the Si270x Class D Audio Amplifier device. Table 16. Class D Audio Amplifier Command Summary Number Name 0x01 POWER_UP 0x10 FUNC_INFO 0x12 SET_PROPERTY 0x13 GET_PROPERTY 0x14 MFP_PIN_CFG 0x15 SET_AUDIO_INPUT_MIXER ...
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... TONE_TWO_AMPLITUDE 0x2906 TONE_TWO_FREQ 0x2907 TONE_TWO_ON_TIME 0x2908 TONE_TWO_OFF_TIME Si2704/05/06/07-A10 Name Set crossover freq between Main Channel and Aux Channel. Set bass shelving filter boost/cut for the Left and Right Channel. Set bass shelving filter corner freq for the Left and Right Channel. ...
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... Buffered reference clock output. Configures 2-Wire address on RST. Multi-function pin 3. PWMDAC left channel analog output on Si2705/07 (Reserved on Si2704/06). PWMDAC right channel analog output on Si2705/07 (Reserved on Si2704/06). Multi-function pin 1. Output select three-level control input: 2.0, 2.1 or line out mode. Right channel power stage supply voltage. ...
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... Multi-function pin 3. PWMDAC left channel analog output on Si2705/07 (Reserved on Si2704/06). PWMDAC right channel analog output on Si2705/07 (Reserved on Si2704/06). Multi-function pin 1. Output select three-level control input: 2.0, 2.1 or line out mode. Right channel power stage supply voltage. Right channel power stage “P” output. ...
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... Si2704/05/06/07-A10 Table 19. Pin Descriptions (Continued) Pin Number Name 29 OUTNR 30 GNDR 31 GNDL 32 OUTNL 34 OUTPL 35 VPPL 40 RST 41 XTLO 42 XTLI 44 VDD 36 Function Right channel power stage “N” output. Right channel power stage ground. Left channel power stage ground. Left channel power stage “N” output. ...
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... Ordering Guide Part Number* Si2704-A10-GM 2.0 EMI Mitigating Class D Power Amplifier Si2704-A10-GQ 2.0 EMI Mitigating Class D Power Amplifier Si2705-A10-GM 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio Si2705-A10-GQ 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio Si2706-A10-GM 2 ...
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... Si2704/05/06/07-A10 8. Package Outline 8.1. 24-Pin QFN Package Figure 27 illustrates the package details for 24-pin QFN package option for the Si2704/05/06/07. Table 20 lists the values for the dimensions shown in the illustration. Table 20. 24-Pin QFN Package Dimensions Dimension Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC D2 2 ...
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... Package Figure 28 illustrates the package details for 48-pin eTQFP package option for the Si2704/05/06/07. Table 21 lists the values for the dimensions shown in the illustration. Si2704/05/06/07-A10 Figure 28. 48-Pin eTQFP Rev. 0.6 39 ...
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... Si2704/05/06/07-A10 Table 21. 48-Pin eTQFP Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC D1 7.00 BSC D2 3.71 3.81 e 0.50 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. This drawing conforms to JEDEC outline MS-026, variation ABC. ...
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... Line 2 Marking Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Work Week Si2704/05/06/07-A10 04 = Si2704 05 = Si2705 06 = Si2706 07 = Si2707 10 = Firmware Revision 1 Revision A Die Internal Tracking Code Pin 1 Identifier Assigned by the Assembly House. Corresponds to the year and work week of the mold date. ...
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... Line 2 Marking Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Work Week 42 Si2704 Si2705 Si2706 Si2707 10 = Firmware Revision 1 Revision A Die Internal Tracking Code Pin 1 Identifier Assigned by the Assembly House. Corresponds to the year and work week of the mold date. ...
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... Si270x Customer Support Site: http://www.silabs.com This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA is required for access to some of these documents. To request access, send mysilabs user name and request for access to AudioInfo@silabs.com. Si2704/05/06/07-A10 Rev. 0.6 43 ...
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... Si2704/05/06/07-A10 OCUMENT HANGE IST Revision 0.4 to Revision 0.5 Updated Table 3 on page 6. Updated Table 4 on page 7. Updated Table 5 on page 7. Updated Table 6 on page 8. Updated Table 11 on page 12. Updated "2. Typical Application Schematic" on page 13. ...
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... N : OTES Si2704/05/06/07-A10 Rev. 0.6 45 ...
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... Si2704/05/06/07-A10 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Audioinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...