SI2107-X-FM SILABS [Silicon Laboratories], SI2107-X-FM Datasheet - Page 28

• Manufacturer Part Number: SI2107-X-FM
• Description: SATELLITE RECEIVER FOR DVB-S/DSS WITH QUICKLOCK AND QUICKSCAN
• Manufacturer: SILABS [Silicon Laboratories]

synchronization lock bit, FSL, is asserted. If lock is not
achieved, the frame synchronizer fail bit, FSF, is
asserted.
The frame synchronizer commences under the control
of the acquisition sequencer.
Following frame synchronization lock, the device
examines the byte stream for a possible 180-degree
phase shift. If an inversion is detected, data are inverted
prior to being output.
6.6. Automatic Gain Control
The Si2107/08/09/10 is equipped with the ability to
adjust signal levels via an automatic gain control (AGC)
loop. This ensures that the noise and linearity
characteristics of the signal path are optimized at all
times. AGC settings can be set at 4 points in the analog
signal chain and 2 points in the digital signal chain.
6.6.1. Analog AGC
System gain is distributed into four independent stages
as shown in Figure 16. The gain range of all stages
combined is over 80 dB. When the AGC search
completes, the AGCL bit is asserted. If an error is
encountered during the AGC search, the AGCF bit is
also set. The AGC search commences under the
control of the acquisition sequencer.
The AGC loop works to automatically adjust the gain of
each stage to minimize the error between a measured
signal power and a desired output level. Signal power is
measured at the output of the ADC using an internal
rms power calculator. The result is stored in a 7-bit
saturating register, AGCPWR. The desired output level
is stored in the AGC threshold register, AGCTH. Signal
power measurements occur at a frequency dictated by
the AGC measurement window size, AGCW. This
LNA
MIXER
VGA1
Figure 16. Analog AGC Control Loop
VGA2
Preliminary Rev. 0.81
LPF
frequency can be described using the following
equation, where fs equals the ADC sampling rate,
ADCSR.
When gain adjustments are made, the device allows up
to 100 µs for the gain changes to settle before
beginning the next measurement.
To facilitate a rapid initial acquisition, Si2107/08/09/10
includes an acquisition mode wherein the measurement
window size is reduced by a factor of 64 when
compared to the normal tracking mode.
During the AGC search, the device is in acquisition
mode, and the gain is adjusted until the measured
signal power crosses the desired threshold or a limit is
reached. If the signal power crosses the threshold
before reaching a limit, the search completes, and the
AGCL bit is asserted. If a gain limit is reached, the
device asserts both the AGCL bit and the AGCF bit.
In the normal tracking mode, the device continuously
measures the input signal power according to the AGC
measurement window size. If the absolute value of the
difference between the AGCTH and AGCPWR exceeds
the value of the AGC tracking threshold, AGCTR, the
AGC loop adjusts gain settings until the AGCPWR level
matches AGCTH.
The AGC gain offset register, AGCO, provides the
ability to apply a static gain offset to the input channel.
Silicon Laboratories will provide the recommended
values for this register. It is possible to read out the
instantaneous settings of each of the four VGAs from
the AGC<n>, <n = 1..4>, registers.
OFFSET
AGC measurement frequency
AGC
A/D
Si2107/08/09/10
AGC Threshold
rms calculator
=
------------------ - Hz
AGCW
f
s
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