SI2107-X-FM SILABS [Silicon Laboratories], SI2107-X-FM Datasheet - Page 24

• Manufacturer Part Number: SI2107-X-FM
• Description: SATELLITE RECEIVER FOR DVB-S/DSS WITH QUICKLOCK AND QUICKSCAN
• Manufacturer: SILABS [Silicon Laboratories]

(INT) as a dedicated interrupt pin via the pin select
register bit, PSEL. The device contains an extensive
collection of interrupt sources that can be individually
masked from the INT pin using the corresponding
interrupt enable register bits, labeled with suffix “_E”.
Thus, the INT output is a logical-OR of all enabled
interrupts. Generation of the channel interrupt on pin
INT can be masked off by using the interrupt enable bit,
INT_EN. Note that interrupt reporting in the register
map is not affected by INT_EN.
The interrupt signal polarity can be configured to be
Receiver lock
Receiver unlock
AGC lock
AGC failure
AGC threshold
Carrier estimation failure
Symbol rate est. lock
Symbol rate est. failure
Symbol timing lock
Symbol timing unlock
Carrier recovery lock
Carrier recovery unlock
Viterbi lock
Viterbi unlock
Frame synchronizer lock
Frame synchronizer unlock
Acquisition fail
C/N measurement complete
Viterbi BER measurement complete
RS measurement complete
Message FIFO empty
Message FIFO full
Message received
Message parity error
Message receive timeout
Short-circuit detect
Over current detect
Blindscan done
Blindscan data ready
Carrier estimation lock
Event
Table 16. Events, Interrupts, and Status Bits
Preliminary Rev. 0.81
Interrupt Bit
MSGPE_I
MSGTO_I
AGCTS_I
MSGR_I
RCVU_I
RSER_I
BSDO_I
RCVL_I
AGCL_I
VTER_I
BSDA_I
CRU_I
OCD_I
STU_I
CRL_I
FSU_I
AQF_I
SCD_I
CEL_I
VTU_I
STL_I
VTL_I
FSL_I
CN_I
FE_I
FF_I
active high or active low using the interrupt polarity bit,
INTP. The interrupt signal type can be configured to be
CMOS output or open-drain/source output using the
interrupt type bit, INTT.
Interrupt bits are set by the device to 1 when an
interrupt occurs. The host clears an interrupt bit by
writing a 1 again, at which time the device resets the
interrupt bit to zero. Table 16 illustrates the interrupt
sources and their associated status, enable, and
interrupt bits.
Enable Bit
MSGPE_E
MSGTO_E
AGCTS_E
MSGR_E
RCVU_E
RSER_E
BSDO_E
RCVL_E
AGCL_E
VTER_E
BSDA_E
CRU_E
OCD_E
AQF_E
SCD_E
CEL_E
STU_E
CRL_E
VTU_E
FSU_E
STL_E
VTL_E
FSL_E
CN_E
FE_E
FF_E
Si2107/08/09/10
AGCTS (0 –> 1)
AGCL (0 –> 1)
RCVL (1 –> 0)
RCVL (0 –>1)
AQF (0 –> 1)
AGCF (0->1)
CEL (0 –> 1)
SRL (0 –> 1)
CRL (0 –> 1)
CRL (1 –> 0)
STL (0 –> 1)
STL (1 –> 0)
VTL (0 –> 1)
VTL (1 –> 0)
FSL (0 –> 1)
FSL (1 –> 0)
SRF (0->1)
CEF(0->1)
Status Bit
BSDO
BSDA
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