73K302L TDK [TDK Electronics], 73K302L Datasheet - Page 6

• Manufacturer Part Number: 73K302L
• Description: Single-Chip Modem
• Manufacturer: TDK [TDK Electronics]

Bell 212A, 103, 202
Single-Chip Modem
PIN DESCRIPTION
DTE USER INTERFACE
NAME
EXCLK
RXCLK
RXD
TXCLK
TXD
ANALOG INTERFACE AND OSCILLATOR
RXA
TXA
XTL1
XTL2
DIP NUMBER
PLCC/PIN
19
23
22
18
21
27
16
2
3
(continued)
O/ Weak
Pull-up
TYPE
O
O
O
I
I
I
I
I
DESCRIPTION
External Clock. This signal is used only in synchronous DPSK
transmission when the external timing option has been selected. In
the external timing mode the rising edge of EXCLK is used to strobe
synchronous DPSK transmit data available on the TXD pin. Also used
for serial control interface.
Receive Clock. The falling edge of this clock output is coincident with
the transitions in the serial received DPSK data output. The rising
edge of RXCLK can be used to latch the valid output data. RXCLK
will be valid as long as a carrier is present. In Bell 202 mode a clock
which is 16 times 1200 or 16 times 150 baud data rate is output.
Received Data Output. Serial receive data is available on this pin.
The data is always valid on the rising edge of RXCLK when in
synchronous mode. RXD will output constant marks if no carrier is
detected.
Transmit Clock.This signal is used only in synchronous DPSK
transmission to latch serial input data on the TXD pin. Data must be
provided so that valid data is available on the rising edge of the
TXCLK. The transmit clock is derived from different sources
depending upon the synchronization mode selection. In Internal Mode
the clock is 1200 Hz generated internally. In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is phase
locked to the RXCLK pin. TXCLK is always active. In Bell 202 mode
the output is a 16 times 1200 baud clock or 16 times 150 baud to
drive a UART.
Transmit Data Input. Serial data for transmission is applied on this
pin. In synchronous modes, the data must be valid on the rising edge
of the TXCLK clock. In asynchronous modes (1200 or 300 baud) no
clocking is necessary. DPSK must be 1200 bit/s +1%, -2.5% or
+2.3%, -2.5% in extended overspeed mode.
Received modulated analog signal input from the telephone line
interface.
Transmit analog output to the telephone line interface.
These pins are for the internal crystal oscillator requiring a 11.0592
MHz parallel mode crystal and two load capacitors to Ground. XTL2
can also be driven from an external clock.
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