ISPGDXTMFAMILY LATTICE [Lattice Semiconductor], ISPGDXTMFAMILY Datasheet - Page 14

• Manufacturer Part Number: ISPGDXTMFAMILY
• Description: In-System Programmable Generic Digital CrosspointTM
• Manufacturer: LATTICE [Lattice Semiconductor]

Table 3. I/O Shift Register Order
The ispGDX devices provide IEEE1149.1a test capabil-
ity and ISP programming through a standard Boundary
Scan Test Access Port (TAP) interface. In addition,
ispGDX devices can be programmed via the Lattice ISP
programming interface using the same TAP serial inter-
face pins.
When the BSCAN/ispEN signal is high the ispGDX de-
vices enable Boundary Scan Test mode. Under this
mode the Boundary Scan data registers for the I/O pins
Figure 7. Boundary Scan I/O Register Cell
Boundary Scan / ISP Programming and Test Options
ispGDX80A
ispGDX120A
ispGDX160/A
DEVICE
SCANIN
(from
previous
cell)
SDI/TDI, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, RESET, Y1/TOE, Y0, I/O B9 .. B0, I/O A19.. A0,
I/O D19 .. D10, SDO/TDO
SDI/TDI, I/O B15 .. B29, I/O C0 .. C29, I/O D0 .. D14, TOE, Y2, Y3, RESET, Y1, Y0, I/O B14 .. B0,
I/O A29.. A0, I/O D29 .. D15, SDO/TDO
SDI/TDI, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, TOE, Y2, Y3, RESET, Y1, Y0, I/O B19 .. B0,
I/O A39.. A0, I/O D39 .. D20, SDO/TDO
Shift DR
M
U
X
M
U
X
M
U
X
Clock DR
D
D
D
Q
Q
Q
I/O SHIFT REGISTER ORDER
Update DR
14
SCANOUT (to next cell)
Specifications ispGDX Family
D
are organized in the order given below. Each
I/O register is structured as shown in Figure 7.
The operation of the boundary scan test circuitry in the
ispGDX160 is dependent on the fuse pattern programmed
into the device. The boundary scan circuitry on the
ispGDX160A, ispGDX120A and ispGDX80A operates
independently of the programmed pattern. This allows
customers using boundary scan test to have full test
capability with only a single BSDL file.
D
Q
Q
Function
Function
Normal
Normal
OE
OE
M
U
X
M
U
X
EXTEST
TOE
I/O Pin
I/O Shift Reg Order/ispGDX