ISPGDXTMFAMILY LATTICE [Lattice Semiconductor], ISPGDXTMFAMILY Datasheet - Page 12

• Manufacturer Part Number: ISPGDXTMFAMILY
• Description: In-System Programmable Generic Digital CrosspointTM
• Manufacturer: LATTICE [Lattice Semiconductor]

The GDF File
The GDF file is a simple text description of the design
function, device and pin parameters. The file has four
parts: device selection, set and constant statements, a
pin section and a connection section. A sample file looks
like this:
//32-bit data exchange from A-bus to B-bus
DESIGN a2bexch
PART ispGDX160-5Q208;
PARAM SECURITY ON;
PARAM PULLUP OFF;
SET busA [dataA0..dataA31];
SET busB [dataB0..dataB31];
BIDI busA {A0..A31} PULLUP SLOWSLEW;
BIDI busB {B0..B31} PULLUP SLOWSLEW;
INPUT [oe0] {C1};
BEGIN
END
This example shows a simple, but complete, 32-bit A-bus
to B-bus data exchange design. Once completed, the
compiler takes over.
Powerful Syntax
Lattice’s ispGDX Design System uses simple, but power-
ful, syntax to easily define a design. The !(bang) operator
controls pin polarity and can be used in both the pin and
connection sections of the design definition. Dot exten-
sions define data inputs, select controls for the 4:1
multiplexor, and control inputs of sequential elements
and tri-state buffers. Dot extensions are .M# (MUX
Input), .S# (MUX Select), and control functions, such as
.CLK, .EN, .OE (shown in adjacent table). Pin Attributes
are assigned in the pin section of the GDF as well.
SLOWSLEW selects the slow slew rate for an output
buffer. PULLUP fixes the on-chip pullup resistor for a
particular pin. The COMB attribute distinguishes the
structure for bidirectional pins. If COMB is used, the input
register, or latch, of an output buffer will be applied to
bidirectional pins.
busA.oe = oe0;
busB.oe = !oe0;
busA.m1 = busB;
busA.s0 = VCC;
busA.s1 = GND;
busB.m0 = busA;
busB.s0 = GND;
busB.s1 = GND;
12
Specifications ispGDX Family
Please consult the ispGDX Development System Manual
for full details.
ispGDX GDF File Dot Extensions
The ispGDX Design System Compiler
After the GDF file is created, the compiler checks the
syntax and provides helpful hints and the location of any
syntax errors. The compiler performs design rule checks,
such as, clock and enable designations, the use of input/
output/BIDI usage, and the proper use of attributes. I/O
connectivity is also checked to ensure polarity, MUX
selection controls, and connections are properly made.
Compilation is completed automatically and report and
programming files are saved.
Reports Generated
When the ispGDX system compiles a design and gener-
ates the specified netlists, the following output files are
created:
Selection
Control
TYPE
MUX
Input
MUX
Report Files
.log - Compiler History
.rpt - Compiler Report
.rt1 - Minimum Delay Timing Report
.rt2 - Maximum Delay Timing Report
Simulation File
.sim - Post-Route Simulation With LAC Format
Netlists
.edo - EDIF Output
.vlo - Verilog Output
.edo - Viewlogic EDIF-format Output
.ifo
.vho - VHDL non-VITAL with Maximum Delays Output
.vhn - VHDL non-VITAL with Maximum Delays Output
.vto - VHDL VITAL Output
- OrCAD Output
DOT EXT.
.CLK
.OE
.M0
.M1
.M2
.M3
.EN
.S0
.S1
MUXA Data input to 4-1 MUX
MUXB Data input to 4-1 MUX
MUXC Data Input to 4-1 MUX
MUXD Data Input to 4-1 MUX
MUX0 Selection input to 4-1 MUX
MUX1 Selection input to 4-1 MUX
Clock for a register signal
Latch enable for a latch signal
Output enable for 3-state output
or bidirectional signal
DESCRIPTION
ispGDX Dot Ext