IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 94

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
Alphabetic Key to Waveform Parameters
Waveforms
No. Name
49 tARYCH
51 tARYCHL ardy Inactive Holding Time
52 tARYLCL ardy Setup Time
87 tAVBL
14 tAVCH
12 tAVLL
66 tAVRL
65 tAVWL
24 tAZRL
45 tCH1CH2 clkoutA Rise Time
68 tCHAV
38 tCHCK
44 tCHCL
67 tCHCSV
18 tCHCSX
22 tCHCTV
64 tCHCV
63 tCHCZ
11 tCHLL
79 tCHRFD
69 tCICOA
70 tCICOB
39 tCKHL
36 tCKIN
40 tCKLH
46 tCL2CL1
50 tCLARX
15 tCLAZ
43 tCLCH
37 tCLCK
42 tCLCL
80 tCLCLX
81 tCLCSL
16 tCLCSV
30 tCLDOX
8
9
3
5
6
7
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tCHDX
tCHLH
tCHSV
tCLAV
tCLAX
tCLDV
Description
ardy Resolution Transition Setup Time
a Address Valid to whb_n/wlb_n Low
ad Address Valid to Clock High
ad Address Valid to ale Low
a Address Valid to rd_n Low
a Address Valid to wr_n Low
ad Address Float to rd_n Active
clkoutA High to A Address Valid
X1 High Time
clkoutA High Time
clkoutA High to lcs_n/usc_n Valid
mcs_n/pcs_n Inactive Delay
Control Active Delay 2
Command Lines Valid Delay (after Float) 75 tDVSH
Command Lines Float Delay
Status Hold Time
ale Active Delay
ale Inactive Delay
clkoutA High to rfsh_n Valid
Status Active Delay
X1 to clkoutA Skew
X1 to clkoutB Skew
X1 Fall Time
X1 Period
X1 Rise time
clkoutA Fall Time
ardy Active Hold Time
ad Address Valid Delay
Address Hold
ad Address Float Delay
clkoutA Low Time
X1 Low Time
clkoutA Period
lcs_n Inactive Delay
lcs_n Active Delay
mcs_n/pcs_n Inactive Delay
Data Hold Time
Data Valid Delay
No. Name Description
71 tCLEV
62 tCLHAV hlda Valid Delay
82 tCLRF
27 tCLRH
25 tCLRL
72 tCLSL
48 tCLSRY srdy Transistion Hold Time
55 tCLTMV Timer Output Delay
83 tCOAOB clkoutA to clkoutB Skew
20 tCVCTV Control Active Delay 1
31 tCVCTX Control Inactive Delay
21 tCVDEX den_n Inactive Delay
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive
19 tDXDL
58 tHVCL
53 tINVCH
54 tINVCL
86 tLCRF
23 tLHAV
10 tLHLL
13 tLLAX
61 tLOCK
84 tLRLL
57 tRESIN
85 tRFCY
29 tRHAV
59 tRHDX
28 tRHLH
26 tRLRH
77 tSHDX
78 tSLDV
47 tSRYCL srdy Transition Setup Time
35 tWHDEX wr_n Inactive to den_n Inactive
34 tWHDX
33 tWHLH
32 tWLWH wr_n Pulse Width
2
4
1
As of Production Version -03
tCLDX
tCLSH
tDVCL
Data in Hold
clkoutA Low to sden Valid
clkoutA High to rfsh_n Invalid
rd_n Inactive Delay
rd_n Active Delay
Status Inactive Delay
clkoutA Low to sclk Low
Data in Setup
Data Valid to SCLK High
den_n Inactive to dt_r_n Low
hld Setup Time
Peripheral Setup Time
drq Setup Time
lcs_n Inactive to rfsh_n Active Delay
ale High to Address Valid
ale Width
ad Address Hold from ALE Inactive
Maximum PLL Lock Time
lcs_n Precharge Pulse Width
res_n Setup Time
rfsh_n Cycle Time
rd_n Inactive to ad Address Active
rd_n High to Data Hold on ad Bus
rd_n Inactive to ale High
rd_n Pulse Width
sclk High to SPI Data Hold
sclk Low SPI Data Hold
Data Hold after wr_n
wr_n Inactive to ale High
Data Sheet