IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 42

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
IMASK (028h) – Interrupt MASK Register.
Master Mode
The interrupt mask register is read/write. Setting a bit in this register is effectively the same as setting the
MSK bit in the corresponding interrupt control register. Setting a bit to 1 masks the interrupt. The
interrupt request is enabled when the corresponding bit is set to 0.
The IMASK register contains 07fdh on reset
Reserved (bits 15 – 3) – Set to 0.
PRM 2-PRM0 (bits 2 - 0) Priority Field Mask. This three-bit field sets the minimum priority
necessary for a maskable interrupt to generate an interrupt. Any maskable interrupt with a
numerically higher value than that contained by these three bits is masked.
Priority Level
Any unmasked interrupt can generate an interrupt if the priority level is set to 7. On the other hand, if
the priority level is set to say 4, only unmasked interrupts with a priority of 0 to 5 are permitted to
generate interrupts.
Reserved (bits 15 – 11)
SPI (bit 10) – Serial Port Interrupt Mask. Setting this bit to 1 is an indication that the asynchronous
serial port interrupt is masked.
15
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15
0
14
Reserved
14
0
13
13
0
12
12
0
11
11
0
SPI WD I4 I3 I2 I1 I0
10
Priority
(High) 0
(Low) 7
10
0
1
2
3
4
5
6
9
9
0
8
8
0
7
As of Production Version -03
7
0
6
PR2 – PR0
6
0
5
0 0 0b
0 0 1b
0 1 0b
0 1 1b
1 0 0b
1 0 1b
1 1 0b
1 1 1b
5
0
4
4
0
3
D1-D0
3
0
2
PRM2 – PRM0
2
Res
1
1
Data Sheet
0
TMR
0