IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 49

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IA186EM-PQF100I-R

Manufacturer Part Number
IA186EM-PQF100I-R
Description
8/16-Bit Microcontrollers
Manufacturer
INNOVASIC [InnovASIC, Inc]
Datasheet

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Part Number:
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Part Number:
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Clock and Power Management
A phase-lock-loop (PLL) and a second programmable system clock output (CLKOUTB) are included in
the clock and power management unit. The internal clock is the same frequency as the crystal but with a
duty cycle of 45% - 55 %, as a worse case, generated by the PLL obviating the need for an x2 external
clock. A power-on reset (POR) resets the PLL.
Figure 2. Crystal Configuration
System Clocks
If required, the internal oscillator can be driven by an external clock source that should be connected to
X1, leaving X2 unconnected.
The clock outputs clkouta and clkoutb may be enabled or disabled individually (Power-Save Control
register (PDCON) bits (11 – 8)). These clock control bits allow one clock output to run at PLL frequency
and the other to run at the power-save frequency.
Figure 3. Organization of Clock
X1,
X2
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
PLL
C
C
1
2
Crystal
Power-Save
(/2 to /128)
Divisor
X1
X2
Am186/188EM
Mux
Processor Internal Clock
Mux
Drive enable
As of Production Version -03
Recommended range of
values for C
C
C
6 +/- 2.5nS
1 =
2 =
Delay
Time
15pF +/- 20%
22pF +/- 20%
Drive enable
1
and C
2
are:
clkouta
clkoutb
Data Sheet

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