IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 19

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
LMCS (0a2h) - Low Memory Chip Select Register configures the Low Memory Chip Select that has
been provided to facilitate access to the interrupt vector table located at 00000h or the bottom of memory.
The lcs_n pin is not active at reset.
The width of the data bus for the lcs_n space should be configured in the AUXCON register before
activating the lcs_n chip select pin, by any write access to the LMCS register.
PCS Address Ranges
Reserved [6:4] (bits 6-4) – Set to 1.
R [3] (bit 3) – Wait State Value. See the following table.
R [2] (bit 2) – Ready Mode. When 0, external ready is required. When 1, external ready is ignored.
But in each case the number of wait states is determined as in the following table.
R [1:0] (bits 1 – 0) – Wait-State Value. See following table. It should be noted that pcs6_n – pcs5_n
and pcs3_n – pcs0_n pins are multiplexed with the programmable I/O pins. And for them to function
as chip selects, the PIO mode and direction settings for these pins must be set to 0 for normal
operation.
PCS3n – PCS0n Wait–State Encoding
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com
PCS0n
PCS1n
PCS2n
PCS3n
Reserved
PCS5n
PCS6n
PCSn Line
R3
0
0
0
0
1
1
1
1
Base Address
Base Address + 256
Base Address + 512
Base Address + 768
N/A
Base Address + 1280
Base Address + 1536
R1
0
0
1
1
0
0
1
1
Low
R0
0
1
0
1
0
1
0
1
As of Production Version -03
Range
Wait States
Base Address + 255
Base Address + 511
Base Address + 767
Base Address + 1023
N/A
Base Address
Base Address
15
0
1
2
3
5
7
9
High
Data Sheet