OR3T125 Agere Systems, OR3T125 Datasheet - Page 95

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Data Sheet
June 1999
FPGA Configuration Modes
There are two options for using the host interrupt
request in configuration mode. The configuration con-
trol register offers control bits to enable the interrupt on
either a bit stream error or to notify the host processor
when the FPGA is ready for more configuration data.
The MPI status register may be used in conjunction
with, or in place of, the interrupt request options. The
status register contains a 2-bit field to indicate the bit
stream error status. As previously mentioned, there is
also a bit to indicate the MPI ’s readiness to receive
another byte of configuration data. A flow chart of the
MPI configuration process is shown in Figure 59. The
MPI status and configuration register bit maps can be
found in the Special Function Blocks section and MPI
configuration timing information is available in the Tim-
ing Characteristics section of this data sheet.
Note: FPGA shown as a memory-mapped peripheral using
Note: FPGA shown as only system peripheral with fixed chip select
Lucent Technologies Inc.
Figure 57. PowerPC /MPI Configuration Schematic
POWERPC
Figure 58. i960 /MPI Configuration Schematic
i960 SYSTEM CLOCK
i960
CS1. Other decoding schemes are possible using
CS1.
signals. For multiperipheral systems, address decoding and/
or latching can be used to implement chip selects.
CLKOUT
RDYRCV
A[27:31]
RD/WR
AD[7:0]
CLKIN
D[7:0]
XINTx
IRQx
ADS
W/R
A26
A25
ALE
BE0
BE1
TA
TS
BI
V
8
8
DD
D[7:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_IRQ
MPI_ALE
MPI_STRB
MPI_BE0
MPI_BE1
CS1
CS0
D[7:0]
A[4:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
CS0
CS1
SERIES 3
SERIES 3
ORCA
FPGA
ORCA
FPGA
DONE
DOUT
CCLK
HDC
DOUT
DONE
LDC
CCLK
INIT
HDC
LDC
INIT
(continued)
TO DAISY-
CHAINED
DEVICES
TO DAISY-
CHAINED
DEVICES
CS0
CS0
5-5761(F)
5-5762(F)
and/or
and
Configuration readback can also be performed via the
MPI when it is in user mode. The MPI is enabled in user
mode by setting the MP_USER bit to 1 in the configura-
tion control register prior to the start of configuration or
through a configuration option. To perform readback,
the host processor writes the 14-bit readback start
address to the readback address registers and sets the
RD_CFG
Readback data is returned 8 bits at a time to the read-
back data register and is valid when the DATA_RDY bit
of the status register is 1. There is no error checking
during readback. A flow chart of the MPI readback
operation is shown in Figure 60. The RD_DATA pin
used for dedicated FPGA readback is invalid during
MPI readback.
ERROR
DONE
Figure 59. Configuration Through MPI
bit to 0 in the configuration control register.
YES
YES
ORCA Series 3C and 3T FPGAs
CONFIGURATION DATA REG
CONTROL REGISTER BITS
READ STATUS REGISTER
READ STATUS REGISTER
WRITE CONFIGURATION
BIT STREAM ERROR?
POWER ON WITH
WRITE DATA TO
DATA_RDY = 1?
VALID M[3:0]
DONE = 1?
INIT = 1?
YES
YES
NO
NO
NO
NO
5-5763(F)
95