OR3T125 Agere Systems, OR3T125 Datasheet - Page 89

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Data Sheet
June 1999
Configuration Data Format
The ORCA Foundry Development System interfaces
with front-end design entry tools and provides tools to
produce a fully configured FPGA. This section dis-
cusses using the ORCA Foundry Development System
to generate configuration RAM data and then provides
the details of the configuration frame format.
The ORCA OR3Cxx and OR3Txxx Series FPGAs are
bit stream compatible.
Using ORCA Foundry to Generate
Configuration RAM Data
The configuration data bit stream defines the I/O func-
tionality, logic, and interconnections within the FPGA.
The bit stream is generated by the development sys-
tem. The bit stream created by the bit stream genera-
tion tool is a series of 1s and 0s used to write the FPGA
configuration RAM. It can be loaded into the FPGA
using one of the configuration modes discussed later.
In the bit stream generator, the designer selects
options that affect the FPGA’s functionality. Using the
output of the bit stream generator, circuit_name.bit,
the development system’s download tool can load the
configuration data into the ORCA series FPGA evalua-
tion board from a PC or workstation.
Alternatively, a user can program a PROM (such as a
Serial ROM or a standard EPROM) and load the FPGA
from the PROM. The development system’s PROM
programming tool produces a file in .mks or .exo for-
mat.
Lucent Technologies Inc.
Configuration Data Frame
Configuration data can be presented to the FPGA in
two frame formats: autoincrement and explicit. A
detailed description of the frame formats is shown in
Figure 52, Figure 53, and Table 32. The two modes are
similar except that autoincrement mode uses assumed
address incrementation to reduce the bit stream size,
and explicit mode requires an address for each data
frame. In both cases, the header frame begins with a
series of 1s and a preamble of 0010, followed by a
24-bit length count field representing the total number
of configuration clocks needed to complete the loading
of the FPGAs.
Following the header frame is a mandatory ID frame.
(Note that the ID frame was optional in the ORCA 2C
and 2C/TxxA Series.)
The ID frame contains data used to determine if the bit
stream is being loaded to the correct type of ORCA
FPGA (i.e., a bit stream generated for an OR3C55 is
being sent to an OR3C55). Error checking is always
enabled for Series 3 devices, through the use of an
8-bit checksum. One bit in the ID frame also selects
between the autoincrement and explicit address modes
for this load of the configuration data.
A configuration data frame follows the ID frame. A data
frame starts with a 01-start bit pair and ends with
enough 1-stop bits to reach a byte boundary. If using
autoincrement configuration mode, subsequent data
frames can follow. If using explicit mode, one or more
address frames must follow each data frame, telling the
FPGA at what addresses the preceding data frame is
to be stored (each data frame can be sent to multiple
addresses).
Following all data and address frames is the postam-
ble. The format of the postamble is the same as an
address frame with the highest possible address value
with the checksum set to all ones.
ORCA Series 3C and 3T FPGAs
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