AM29SL400C SPANSION [SPANSION], AM29SL400C Datasheet
AM29SL400C
Related parts for AM29SL400C
AM29SL400C Summary of contents
Page 1
... AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number Am29SL400C Revision A Amendment +5 Issue Date March 3, 2005 ...
Page 2
This Page Left Intentionally Blank. ...
Page 3
... Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data Publication# Am29SL400C Rev: A Amendment+5 ...
Page 4
... General Description The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data ap- pears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt V supply ...
Page 5
... Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA Packages ............6 Pin Configuration Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. Am29SL400C Device Bus Operations ......................... 9 Word/Byte Configuration ........................................................9 Requirements for Reading Array Data .................................9 Writing Commands/Command Sequences ....................... 10 Program and Erase Operation Status ................................. 10 Standby Mode ............................................................................ 10 Automatic Sleep Mode ............................................................ 10 RESET#: Hardware Reset Pin ...
Page 6
... V -100R CC = 1.65–2 100 100 35 Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic STB Timer Am29SL400C -110 -120 -150 110 120 110 120 45 50 DQ0–DQ15 (A-1) Input/Output Buffers Data Latch STB Y-Decoder Y-Gating Cell Matrix ...
Page 7
Connection Diagrams A15 1 A14 2 A13 3 A12 4 A11 5 6 A10 WE# 11 RESET RY/BY A17 ...
Page 8
Connection Diagram A6 B6 A13 A12 WE# RESET RY/BY A17 Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory prod- ...
Page 9
Pin Configuration A0–A17 = 18 addresses DQ0–DQ14= 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = ...
Page 10
... T = Top Sector B = Bottom Sector Valid Combinations for FBGA Packages Order Number AM29SL400CT100R, AM29SL400CB100R AM29SL400CT110, EC, EI, AM29SL400CB110 ED, EF AM29SL400CT120, AM29SL400CB120 AM29SL400CT150, AM29SL400CB150 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of spe- cific valid combinations and to check on newly re- leased combinations ...
Page 11
... The com- mand register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the ad- Table 1. Am29SL400C Device Bus Operations Operation CE# Read L ...
Page 12
Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE and OE For ...
Page 13
... SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Table 3. Am29SL400CB Bottom Boot Block Sector Address Table Sector A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 0 1 ...
Page 14
... When all necessary bits have been set as required, the pro- gramming equipment may then read the corre- sponding identifier code on DQ7–DQ0. Table 4. Am29SL400C Autoselect Codes (High Voltage Method) Description Mode CE# OE# Manufacturer ID: AMD ...
Page 15
START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
Page 16
START RESET (Note 1) Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 2. Temporary Sector ...
Page 17
The reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. This resets the device to reading array data (also applies to ...
Page 18
Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase ...
Page 19
When the Embedded Erase algorithm is complete, the device returns to reading array data and ad- dresses are no longer latched. The system can deter- mine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer ...
Page 20
... Command Definitions Table 5. Am29SL400C Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector Protect Verify 4 (Note 9) Byte Word Program ...
Page 21
DQ7, RY/BY#, and DQ6 each offer a method for de- termining whether a program or erase operation is complete or in progress. These three bits are dis- cussed first. DQ7: Data# Polling The ...
Page 22
Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode the standby mode. Table 6 on page 22 shows the outputs ...
Page 23
START Read DQ7–DQ0 (Note 1) Read DQ7–DQ0 No Toggle Bit = Toggle? Yes No DQ5 = 1? Yes (Notes Read DQ7–DQ0 1, 2) Twice Toggle Bit No = Toggle? Yes Program/Erase Operation Not Program/Erase Complete, Write Operation Complete Reset Command ...
Page 24
Operation Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Erase Suspended Sector Erase Suspend Reading within Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the ...
Page 25
Operating Ranges Commercial (C) Devices Ambient Temperature ( 0°C to +70°C A Industrial (I) Devices Ambient Temperature ( –40°C to +85° Supply ...
Page 26
DC Characteristics CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes ...
Page 27
DC Characteristics (Continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
Page 28
Test Conditions Device Under Test C Figure 11. Test Setup Key to Switching Waveforms WAVEFORM Don’t Care, Any Change Permitted 2.0 V 1.0 V Input 0.0 V Figure 12. Input Waveforms and Measurement Levels ...
Page 29
AC Characteristics Read Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
Page 30
AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...
Page 31
AC Characteristics Word/Byte Configuration (BYTE#) Parameter JEDEC Std t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# BYTE# ...
Page 32
AC Characteristics Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data ...
Page 33
AC Characteristics Program Command Sequence (last two cycles Addresses 555h CE Data RY/BY VCS Notes program address program data Illustration ...
Page 34
AC Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...
Page 35
AC Characteristics t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
Page 36
AC Characteristics Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Temporary Sector ...
Page 37
AC Characteristics RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# * For sector protect For sector unprotect ...
Page 38
AC Characteristics Alternate CE# Controlled Erase/Program Operations Parameter Description JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH ...
Page 39
AC Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written, ...
Page 40
Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 typicals assume ...
Page 41
Physical Dimensions TS048—48-Pin Standard TSOP March 3, 2005 Dwg rev AA; 10/99 39 ...
Page 42
Physical Dimensions FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA Package Dwg rev AF; 10/99 March 3, 2005 ...
Page 43
Revision Summary Revision A (August 14, 2002) Initial Release. Revision A+1 (August 28, 2002) Sector Protection/Unprotection Changed beginning of second paragraph from, “The primary method....” to read, “Sector protection/un- protection.” Deleted third paragraph. FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 ...
Page 44
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated ...