AM29PDLI27H SPANSION [SPANSION], AM29PDLI27H Datasheet - Page 43

• Manufacturer Part Number: AM29PDLI27H
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

Legend:
DYB = Dynamic Protection Bit
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
1. See
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of
June 30, 2003
Command
(Notes)
Reset
SecSi Sector Entry 3
SecSi Sector Exit
SecSi Protection
Bit Program (5, 6)
SecSi Protection
Bit Status
Password Program
(5, 7, 8)
Password Verify
(6, 8, 9)
Password Unlock
(7, 10, 11)
PPB Program (5,
6, 12)
PPB Status
All PPB Erase (5,
6, 13, 14)
PPB Lock Bit Set
PPB Lock Bit
Status (15)
DYB Write (7)
DYB Erase (7)
DYB Status (6)
PPMLB Program
(5, 6, 12)
PPMLB Status (5)
SPMLB Program
(5, 6, 12)
SPMLB Status (5)
write operations.
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0
in cycle 6, program command must be issued and verified again.
password.
Table 1
for description of bus operations.
1 XXX
4
6
4
4
4
7
6
4
6
3
4
4
4
4
6
4
6
4
Addr Data Addr Data Addr Data
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
F0
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
Table 14. Sector Protection Command Definitions
A D V A N C E
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
C8
88
90
60
60
38
28
60
90
60
78
58
48
48
58
60
60
60
60
PWA[0-3]
(SA)WP
(SA)WP
XX[0-3]
PWA[0]
Addr
Am29PDL127H
OW
OW
WP
XX
SA
SA
SA
SA
PL
PL
SL
SL
I N F O R M A T I O N
PWD[0-3]
Bus Cycles (Notes 1-4)
PWD[0]
PD[0-3]
RD(0)
RD(0)
RD(1)
RD(0)
RD(0)
RD(0)
Data
X1
X0
00
68
68
60
68
68
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits
A22:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010) (Note16)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
15. DQ1 = 1 if PPB locked, 0 if unlocked.
16. For PDL128G and PDL640G, the WP address is 0111010. The
addresses 0-3.
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command
must be issued and verified again. Before issuing erase
command, all PPBs should be programmed to prevent PPB
overerasure.
EP address (PPB Erase Address) is 1111010.
(SA)WP
PWA[1]
Addr
(SA)
OW
PL
SL
PWD[1]
Data
48
48
40
48
48
(SA)WP
(SA)WP
PWA[2]
Addr
OW
PL
SL
PWD[2]
RD(0)
RD(0)
RD(0)
RD(0)
RD(0)
Data
PWA[3]
Addr
PWD[3]
Data
41