AM29PDLI27H SPANSION [SPANSION], AM29PDLI27H Datasheet - Page 15

• Manufacturer Part Number: AM29PDLI27H
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device re-
quires standard access time (t
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
150 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Note that during automatic sleep mode, OE# must be
at V
sleep mode specification. I
tics
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
June 30, 2003
CC3
IH
IO
.) If CE# and RESET# are held at V
± 0.3 V, the device will be in the standby mode, but
table represents the automatic sleep mode current
IH
in the
before the device reduces current to the stated
DC Characteristics
CC5
in the
A D V A N C E
table represents the
CE
) for read access
DC Characteris-
IH
, but not within
RP
ACC
Am29PDL127H
, the
+
I N F O R M A T I O N
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
Algorithms). The system can read data t
RESET# pin returns to V
Refer to the
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins (except for RY/BY#) are
placed in the highest Impedance state
IL
but not within V
READY
AC Characteristic
(during Embedded Algorithms). The
SS
±0.3 V, the standby current will
READY
IH
.
IH
, output from the device is
(not during Embedded
tables for RESET# pa-
CC4
SS
). If RESET# is held
±0.3 V, the device
RH
after the
13