AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 13

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory.
If the system asserts V
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
eration. Note that V
for operations other than accelerated programming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the
lect Command Sequence
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
but the standby current will be greater. The device re-
quires standard access time (t
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the
CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
12
HH
IH
CC
.) If CE# and RESET# are held at V
from the ACC pin returns the device to normal op-
± 0.3 V, the device will be in the standby mode,
DC Characteristics
HH
HH
must not be asserted on ACC
Autoselect Mode
on this pin, the device auto-
sections for more informa-
CE
table represents the
) for read access
IH
, but not within
and
P R E L I M I N A R Y
CC
± 0.3 V.
Autose-
Am29PDL128G
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Note that during automatic sleep mode, OE# must be
at V
sleep mode specification. ICC5 in the
tics
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (ICC4). If RESET# is
held at V
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
Algorithms). The system can read data t
RESET# pin returns to V
Refer to the
rameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins (except for RY/BY#) are
placed in the high impedance state.
table represents the automatic sleep mode current
IH
before the device reduces current to the stated
READY
IL
but not within V
AC Characteristics
(during Embedded Algorithms). The
READY
IH
.
IH
SS
, output from the device is
±0.3 V, the standby cur-
(not during Embedded
tables for RESET# pa-
SS
±0.3 V, the device
DC Characteris-
July 29, 2002
RH
after the
RP
ACC
, the
+