AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 12

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

inputs (assuming the addresses have been stable for
at least t
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 8 words, or 4 double words, with the ap-
propriate page being selected by the higher address
bits A21–A2 and the LSB bits A1–A0 (in the double
word mode) and A1 to A-1 (in the word mode) deter-
mining the specific word/double word within that page.
This is an asynchronous operation with the micropro-
cessor supplying the specific word or double word lo-
cation.
The random or initial page access is equal to t
t
the locations specified by the microprocessor falls
within that page) is equivalent to t
deasserted and reasserted for a subsequent access,
the access time is t
the device and OE# is the output control and should
be used to gate data to the output inputs if the device
is selected. Fast page mode accesses are obtained by
keeping A21–A2 constant and changing A1 to A0 to
select the specific double word, or changing A1 to A-1
to select the specific word, within that page.
July 29, 2002
CE
Double Word 0
Double Word 1
Double Word 2
Double Word 3
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
and subsequent page read accesses (as long as
Word
Table 2. Page Select, Double Word Mode
Word
ACC
Table 3. Page Select, Word Mode
–t
OE
time).
A1
ACC
0
0
0
0
1
1
1
1
or t
A1
CE
0
0
1
1
. Here again, CE# selects
A0
0
0
1
1
0
0
1
1
PACC
. When CE# is
P R E L I M I N A R Y
A0
0
1
0
1
A-1
0
1
0
1
0
1
0
1
ACC
Am29PDL128G
or
Simultaneous Operation
The device is capable of reading data from one bank
of memory while a program or erase operation is in
progress in another bank of memory (simultaneous
operation), in addition to the conventional features
(read, program, erase-suspend read, and erase-sus-
pend program). The bank selected can be selected by
bank addresses (A21–A19) with zero latency.
The simultaneous operation can execute multi-func-
tion mode in the same bank.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
For program operations, the WORD# pin determines
whether the device accepts program data in double
words or words. Refer to “Word/Double Word Configu-
ration” for more information.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once a bank enters the Un-
lock Bypass mode, only two write cycles are required
to program a double word or word, instead of four. The
“Double Word/Word Program Command Sequence”
section has details on programming data to the device
using both standard and Unlock Bypass command se-
quences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
space that each sector occupies. A “bank address” is
the address bits required to uniquely select a bank.
Similarly, a “sector address” refers to the address bits
required to uniquely select a sector. The “Command
Definitions” section has details on erasing a sector or
the entire chip, or suspending/resuming the erase op-
eration.
I
tive current specification for the write mode. The
Characteristics
tables and timing diagrams for write operations.
CC2
in the DC Characteristics table represents the ac-
IL
Bank 1
Bank 2
Bank 3
Bank 4
, and OE# to V
Bank
Table 4. Bank Select
section contains timing specification
IH
Table 5
.
indicates the address
001, 010, 011
100, 101, 110
A21–A19
000
111
AC
11