74AUP1G373GF,132 NXP Semiconductors, 74AUP1G373GF,132 Datasheet - Page 3

• Manufacturer Part Number: 74AUP1G373GF,132
• Description: IC LATCH D-TYPE 6-XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1G373GF,132

• Logic Type: D-Type Transparent Latch
• Package / Case: 6-XSON, SOT891
• Circuit: 1:1
• Output Type: Tri-State
• Voltage - Supply: 0.8 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 2.5ns
• Current - Output High, Low: 4mA, 4mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: 74AUP
• Polarity: Non-Inverting
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 22.1 ns at 1.1 V to 1.3 V, 12.3 ns at 1.4 V to 1.6 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 50 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP1G373GF-H; 74AUP1G373GF-H; 935281332132

NXP Semiconductors
6. Pinning information
Table 3.
7. Functional description
Table 4.
[1]
74AUP1G373
Product data sheet
Symbol
LE
GND
D
Q
V
OE
Operating modes
Enable and read register (transparent
mode)
Latch and read register
Latch register and disable outputs
Fig 4.
CC
H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition;
X = Don’t care;
Z = high-impedance OFF-state.
GND
LE
D
Pin configuration SOT363
Pin description
Function table
1
2
3
74AUP1G373
6.1 Pinning
6.2 Pin description
001aae250
[1]
6
5
4
Pin
1
2
3
4
5
6
OE
V
Q
CC
All information provided in this document is subject to legal disclaimers.
Fig 5.
Input
OE
L
L
L
L
H
GND
Description
latch enable input (active HIGH)
ground (0 V)
data input
latch output
supply voltage
output enable input (active LOW)
Rev. 4 — 15 July 2010
Pin configuration SOT886
LE
D
Transparent top view
74AUP1G373
1
2
3
LE
H
H
L
L
X
001aae251
6
5
4
OE
V
Q
CC
Low-power D-type transparent latch; 3-state
D
L
H
l
h
X
Fig 6.
Internal latch
L
H
L
H
X
GND
74AUP1G373
Pin configuration SOT891,
SOT1115 and SOT1202
LE
D
Transparent top view
74AUP1G373
1
2
3
© NXP B.V. 2010. All rights reserved.
001aae252
6
5
4
L
Output
Q
L
H
H
Z
OE
V
Q
CC
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