74AUP1G373 NXP Semiconductors, 74AUP1G373 Datasheet

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74AUP1G373

Manufacturer Part Number
74AUP1G373
Description
Low-power D-type transparent latch 3-state
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
74AUP1G373GW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While
the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is
LOW, the latch stores the information that was present at the D-input one set-up time
preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of
the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the
high-impedance OFF-state. Operation of input pin OE does not affect the state of the
latch.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
CC
74AUP1G373
Low-power D-type transparent latch; 3-state
Rev. 03 — 9 January 2008
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114E Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101-C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
www.DataSheet4U.com
Product data sheet
OFF
.

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74AUP1G373 Summary of contents

Page 1

... Rev. 03 — 9 January 2008 1. General description The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH-to-LOW transition of pin LE ...

Page 2

... Package Temperature range Name 74AUP1G373GW +125 C 74AUP1G373GM +125 C 74AUP1G373GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G373GW 74AUP1G373GM 74AUP1G373GF 5. Functional diagram 001aae247 Fig 1. Logic symbol 74AUP1G373_3 Product data sheet Low-power D-type transparent latch; 3-state ...

Page 3

... LOW) Input Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com 74AUP1G373 GND 001aae252 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) Internal latch Output ...

Page 4

... Power-down mode 0 3 Conditions Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Min Max Unit 0.5 +4 [1] 0.5 +4 [1] 0.5 +4 ...

Page 5

... V = GND Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state Min Typ Max ...

Page 6

... Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state Min Typ Max ...

Page 7

... GND GND. CC Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state Min Typ Max ...

Page 8

... Product data sheet Figure 25 C [1] Min Typ [2] Figure 7 - 21.4 2.8 6.6 2.4 4.6 1.9 3.7 1.8 2.9 1.5 2.5 [2] Figure 8 - 20.3 2.7 6.2 2.3 4.4 1.8 3.5 1.5 2.6 1.3 2.2 [3] Figure 10 - 17.9 3.2 5.1 2.6 3.8 2.2 3.3 2.0 2.7 1.9 2.5 [4] Figure 10 - 9.4 2.9 4.2 2.2 3.2 2.2 3.0 1.6 2.2 1.9 2.6 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 11 +125 C Max Min Max Min (85 C) (85 C) (125 13.5 2.6 13.8 2.6 7.8 2.1 8.3 2.1 6.2 1.6 6.7 1.6 4.1 1.5 4.5 1.5 3.5 1.2 4.0 1 13.6 2.5 14.0 2.5 7.6 2.0 8.5 2.0 5.8 1.5 6.7 1.5 4.0 1.3 4.4 1.3 3.3 1.1 3.8 1 ...

Page 9

... Product data sheet …continued Figure 25 C [1] Min Typ [2] Figure 7 - 24.4 3.0 7.5 2.6 5.3 2.5 4.3 2.0 3.5 1.8 3.1 [2] Figure 8 - 23.3 2.9 7.1 2.5 5.0 2.3 4.1 1.9 3.1 1.7 2.8 [3] Figure 10 - 21.2 3.7 6.0 3.1 4.5 2.7 3.9 2.4 3.3 2.3 3.1 [4] Figure 10 - 11.3 3.9 5.3 3.0 4.1 3.2 4.2 2.3 3.0 3.0 3.8 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 11 +125 C Max Min Max Min (85 C) (85 C) (125 15.3 2.7 15.9 2.7 9.0 2.2 9.4 2.2 6.9 2.1 7.3 2.1 4.8 1.8 5.3 1.8 4.2 1.7 4.6 1 15.4 2.7 16.1 2.7 8.8 2.1 9.5 2.1 6.6 2.0 7.3 2.0 4.7 1.6 5.2 1.6 4.0 1.4 4.4 1 ...

Page 10

... Product data sheet …continued Figure 25 C [1] Min Typ [2] Figure 7 - 27.3 3.5 8.3 3.1 5.9 2.6 4.8 2.5 3.9 2.2 3.6 [2] Figure 8 - 26.1 3.3 7.9 3.0 5.6 2.5 4.6 2.3 3.6 2.1 3.2 [3] Figure 10 - 24.6 4.1 6.8 3.5 5.1 3.1 4.4 2.8 3.7 2.6 3.5 [4] Figure 10 - 13.1 4.9 6.5 3.9 5.0 4.2 5.3 3.0 3.8 4.1 5.0 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 11 +125 C Max Min Max Min (85 C) (85 C) (125 16.9 3.2 17.5 3.2 9.6 2.7 10.5 2.7 7.6 2.2 8.5 2.2 5.5 2.2 5.9 2.2 4.9 1.8 5.5 1 17.3 3.0 18.0 3.0 9.7 2.5 10.7 2.5 7.4 2.2 8.3 2.2 5.3 2.0 5.9 2.0 4.6 1.8 5.1 1 ...

Page 11

... Product data sheet …continued Figure 25 C [1] Min Typ [2] Figure 7 - 35.9 4.0 10.6 3.6 7.5 3.5 6.2 3.3 5.1 3.0 4.7 [2] Figure 8 - 34.8 3.9 10.2 3.5 7.2 3.3 5.9 3.1 4.8 2.9 4.4 [3] Figure 10 - 34.5 5.5 9.1 4.6 6.7 4.2 5.7 3.6 4.9 3.4 4.7 [4] Figure 10 - 19.2 8.0 9.9 6.3 7.7 7.3 8.7 5.2 6.2 7.5 8.8 Figure 8 - 4.0 - 0.7 - 0.5 - 0.4 - 0.3 - 0.2 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 11 +125 C Max Min Max Min (85 C) (85 C) (125 22.1 3.7 23.3 3.7 12.3 3.5 13.6 3.5 9.5 3.2 10.5 3.2 6.9 2.9 7.6 2.9 6.4 2.9 7.2 2 22.2 3.7 23.5 3.7 12.4 3.4 13.7 3.4 9.5 3.0 10.5 3.0 6.8 2.7 7.5 2.7 6.1 2.6 7.0 2 16.2 4.9 16.2 4.9 9.9 4.2 10.5 4.2 7.9 3.7 8.6 3.7 6 ...

Page 12

... 74AUP1G373_3 Product data sheet Low-power D-type transparent latch; 3-state …continued Figure 25 C [1] Min Typ Figure 9 - 4.6 - 0.9 - 0 0.1 Figure 9 - 4.0 - 1.2 - 0.7 - 0.6 - 0.4 - 0.3 - 4.6 - 0.9 - 0.6 - 0.4 - 0.2 - 0.1 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com 11 +125 C Max Min Max Min (85 C) (85 C) (125 C) (125 2.2 - 2.2 - 1.4 - 1.4 - 1.0 - 1.0 - 0.6 - 0.6 - 0 2.7 - 2.7 - 1 ...

Page 13

... W where input M GND t PHL output Table 9. Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 11 +125 C Max Min Max Min (85 C) (85 C) (125 ...

Page 14

... I D input V M GND GND Table 9. Input 0 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state t PLH 001aae254 001aae255 3 © NXP B.V. 2008. All rights reserved ...

Page 15

... GND outputs enabled disabled Table 10. Output Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state t PZL PZH V M outputs outputs enabled mna644 0 0. ...

Page 16

... V EXT [ PLH open = for measuring propagation delays, setup and hold times and pulse width R L Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com PHL PZH PHZ PZL GND 2 V © NXP B.V. 2008. All rights reserved. ...

Page 17

... scale 2.2 1.35 2.2 0.45 1.3 0.65 1.8 1.15 2.0 0.15 REFERENCES JEDEC JEITA SC-88 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state detail 0.25 0.2 0.2 0.1 0.15 EUROPEAN ISSUE DATE PROJECTION © NXP B.V. 2008. All rights reserved. ...

Page 18

... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 4 ( EUROPEAN PROJECTION © NXP B.V. 2008. All rights reserved. SOT886 ISSUE DATE 04-07-15 04-07- ...

Page 19

... scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 4 ( EUROPEAN ISSUE DATE PROJECTION © NXP B.V. 2008. All rights reserved. SOT891 05-04-06 07-05- ...

Page 20

... Low-power D-type transparent latch; 3-state Data sheet status Change notice Product data sheet - 11: Propagation delay, set-up and hold and power dissipation capacitance values Product data sheet - Product data sheet - Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com Supersedes 74AUP1G373_2 74AUP1G373_1 - © NXP B.V. 2008. All rights reserved ...

Page 21

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 9 January 2008 74AUP1G373 www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...

Page 22

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: 74AUP1G373_3 All rights reserved. Date of release: 9 January 2008 ...

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